PCM3168APAP datasheet(7/66 Pages) TI

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PCM3168A

PCM3168A-Q1

www.ti.com ......................................................................................................................................................................................... SBAS452 – SEPTEMBER 2008

ELECTRICAL CHARACTERISTICS: DAC Characteristics (continued)

All specifications at TA = +25°C, VCCAD1 = VCCAD2 = VCCDA1 = VCCDA2 = 5 V, VDD1 = VDD2 = 3.3 V, fS = 48 kHz,

SCKI = 512 fS, 24-bit data, Sampling Mode = Auto for ADC and DAC, and Interface Mode = Slave for ADC and DAC, unless

otherwise noted.

PCM3168A, PCM3168A-Q1

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

ANALOG OUTPUT

1.6 ×

Output voltage

Differential

VPP

VCCDA1

0.5 ×

Center voltage

VCCDA1

To ac-coupled GND(3)

Ω

Load impedance

To dc-coupled GND(3)

Ω

f = 20 kHz

–0.04

Low-pass filter frequency response

f = 44 kHz

–0.18

DIGITAL FILTER PERFORMANCE(4)

Sharp roll-off

Passband (single, dual)

0.454 × fS

Passband (quad)

0.432 × fS

Stop band (single, dual)

0.546 × fS

Stop band (quad)

0.569 × fS

Passband ripple

< 0.454 × fS, 0.432 × fS

±0.0018

Stop band attenuation

> 0.546 × fS, 0.569 × fS

–75

DIGITAL FILTER PERFORMANCE

Slow roll-off

Passband

0.328 × fS

Stop band

0.673 × fS

Passband ripple

< 0.328 × fS

±0.0013

Stop band attenuation

> 0.673 × fS

–75

DIGITAL FILTER PERFORMANCE(4)

Group delay time (single, dual)

28/fS

sec

Group delay time (quad)

19/fS

sec

De-emphasis error

±0.1

POWER-SUPPLY REQUIREMENTS

VCCxx1/2

4.5

5.0

5.5

VDC

Voltage range

VDD1/2

3.0

3.3

3.6

VDC

fS = 48 kHz/ADC, fS = 48 kHz/DAC

162

210

ICC fS = 96 kHz/ADC, fS = 192 kHz/DAC

162

Full power-down(5)

300

µA

Supply current

fS = 48 kHz/ADC, fS = 48 kHz/DAC

106

130

IDD fS = 96 kHz/ADC, fS = 192 kHz/DAC

127

Full power-down(5)

µA

fS = 48 kHz/ADC, fS = 48 kHz/DAC

1160

1480

fS = 96 kHz/ADC, fS = 192 kHz/DAC

1230

Power dissipation

fS = 48 kHz/ADC, Power-down/DAC

660

Power-down/ADC, fS = 48 kHz/DAC

633

Full power-down(5)

1.67

(3)

Allowable minimum input resistance of differential to single-ended converter with D to S Gain = G is calculated as (1 + 2G)/(1 + G) × 5k

for ac-coupled and (1+ 0.9G)/(1 + G) × 15k for dc-coupled connection, refer to Figure 62 and Figure 63 of the Application Information

section.

(4)

Exclude single and dual at 128 fS, 192 fS system clock and quad at 256 fS to 768 fS system clock, and specifications for quad, single,

and dual are respectively applied in reverse for them.

(5)

Halt SCKI, BCKAD, BCKDA, LRCKAD, and LRCKDA.

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