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PCM3168APAP Datasheet(PDF) 26 Page - Texas Instruments |
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PCM3168APAP Datasheet(HTML) 26 Page - Texas Instruments |
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26 / 66 page ![]() LRCKDA (Slave) BCKDA Left-JustifiedMode DIN1 (Dual) I SMode 2 DIN1 (Dual) Left-JustifiedMode DIN1/2 (Quad) I SMode 2 DIN1/2 (Quad) 1/f (256BCKsatDualRate,128BCKsatQuadRate) S 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 23 22 0 23 22 1 0 23 22 1 0 23 22 1 0 23 22 23 22 1 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 23 22 0 23 22 1 0 1 0 1 0 23 22 23 22 1 0 23 22 23 22 Ch1 32BCKs Ch2 32BCKs Ch3 32BCKs Ch4 32BCKs Ch5 32BCKs Ch6 32BCKs Ch7 32BCKs Ch8 32BCKs Ch1/Ch5 32BCKs Ch2/Ch6 32BCKs Ch3/Ch7 32BCKs Ch4/Ch8 32BCKs AUDIO INTERFACE TIMING BCKAD/DA (Input) 1.4V 1.4V 1.4V 0.5 VDD ´ t LRS t DOD LRCKAD/DA (Input) DOUT1/2/3 DIN1/2/3/4 t DIH t LRH t DIS t BCH t BCL t BCY PCM3168A PCM3168A-Q1 SBAS452 – SEPTEMBER 2008 ......................................................................................................................................................................................... www.ti.com Figure 41. Audio Data Format: 24-Bit High-Speed TDM Format (SCKI = 128 fS, 256 fS, DAC, and Slave Mode Only) Figure 42 through Figure 45 describe the detailed interface timing specifications. Figure 42. Audio Interface Timing Requirements for Left-Justified, Right-Justified, and I2S Data Formats (Slave Mode) Table 9. Timing Requirements for Figure 42(1) SYMBOL DESCRIPTION MIN TYP MAX UNIT tBCY BCKAD/DA cycle time 75 ns tBCH BCKAD/DA pulse width high 35 ns tBCL BCKAD/DA pulse width low 35 ns tLRS LRCKAD/DA setup time to BCKAD/DA rising edge 10 ns tLRH LRCKAD/DA hold time to BCKAD/DA rising edge 10 ns tDIS DIN1/2/3/4 setup time to BCKDA rising edge 10 ns tDIH DIN1/2/3/4 hold time to BCKDA rising edge 10 ns tDOD DOUT1/2/3 delay time from BCKAD falling edge 0 30 ns (1) Load capacitance of output is 20 pF. 26 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): PCM3168A PCM3168A-Q1 |
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