7

3672A–CNFG–1/08

AT18F010/002/040/080 [Preliminary]

6.6

CEO

Chip Enable Output for configuration download. This output goes Low when the internal address

counter of the device has reached its maximum value which signals that all configuration data is

being clocked out of the device. In a daisy chain of AT18F Series devices, the CEO pin of one

device must be connected to the CE input of the next device in the chain. It will stay Low as long

as CE is Low and OE is High. It will then follow CE until OE goes Low; thereafter, CEO will stay

High until the entire memory device is read again.

6.7

TMS

JTAG Mode Control Input. The state of TMS with the rising edge of TCK determines the state

transitions of the Test Access Port (TAP) controller. TMS has an internal 50 K

Ω weak pull-up to

V

6.8

TCK

JTAG Clock Input. This pin is the JTAG clock input to the TAP controller of the device.

6.9

TDI

JTAG Serial Data Input. This pin is the serial input to all JTAG instructions and data registers. An

internal 50 K

Ω weak pull-up to V

6.10

TDO

JTAG Serial Data Output. This pin is the serial output to all JTAG instruction and data registers.

An internal 50 K

Ω weak pull-up to V

6.11

VCCINT

+3.3V supply voltage for internal logic.

6.12

NC

No Connect Pin. This pin is not connected to any internal logic of the device and can be left

floating.

6.13

VCCO

Supply voltage for I/O drivers (1.8V, 3.3V, or 3.3V).

6.14

VCCJ

Supply voltage for JTAG I/O drivers (1.8V, 3.3V, or 3.3V).

6.15

GND

Power supply ground.

7.

Standby Mode

The AT18F Series Configurators enter a low-power standby mode whenever the JTAG mode is

inactive and CE is asserted High. In this mode, the AT18F Configurator consumes less than 1

mA of current at 3.3V. The output remains in a high-impedance state regardless of the state of

the OE input.