TSS463B datasheet(9/59 Pages) ATMEL

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TSS463B

4102E–AUTO–12/04

The master device provides the serial clock on the TxD pin and is still connected to

SCLK pin of the slave device.

Then, the RxD replaces the MOSI and MISO pins and is a bidirectional pin. To achieve

a correct communication, the user should add a few gates to connect the master RxD

pin to the MOSI-MISO slave pins.

Figure 5 proposes two 3-state buffers controlled by the master through a general pur-

pose I/O pin.

It is obvious that, in this Intel SPI mode, the master cannot monitor the ’0xAA and

0x55’synchronization bytes while sending the address and control bytes. It is the only

exception of this mode compared with the Motorola SPI mode.

SCI Mode

The SCI mode is the third type of interface. The TSS463B enters this mode if the Initial-

ization Sequence contains (first two bytes received) ’0x00, 0xFF’.

The SCI is compatible with a 9-bits SCI protocol. The interface is implemented for slave-

mode only (the TSS463B cannot generate SCI frames by itself).

The SCI interface allows an interconnection of several CPUs and peripherals on the

same printed circuit board.

The SCI mode interface consists of 4 pins: separate wires are required for data and

clock, so the clock is not included in the data stream as shown in Figure 7. One pin is

needed for the serial clock (SCLK), two pins for data exchange MOSI and MISO and

one pin for Slave Select (SS).

Figure 6. SCI Data Stream

SCLK: Serial Clock

The master device provides the serial clock for the slave devices. Data is transferred

synchronously with this clock in both directions. The master and the slave devices

exchange a data byte during a nine clock pulses sequence. However, the TSS463B will

only monitor 8 bits on its MOSI line and send 9 bits on its MISO line.

MOSI: Master Out Slave In

The MOSI pin is the master device data output (CPU) and the slave device data input

(TSS463B). Data is transferred serially from the master to the slave on this line; least

significant bit (LSB) first, most significant bit (MSB) last. The TSS463B will only monitor

8 bits starting from the LSB to MSB-1.

MISO: Master In Slave Out

The MISO pin is configured as the slave device data output (TSS463B) and as master

device data input (CPU). When the slave device is not selected (SS = 1), this pin is in

high impedance state. The value of the MSB (9

th bit) sent on the MISO pin will always be

’1’and should not be used by the master.

SS: Slave Select

The SS pin is the slave chip select. It is low active. A low state on the Slave Select input

allows the TSS463B to accept data on the MOSI pin and send data on the MISO pin.

MOSI

MISO

0x55

SCLK

SCI 9 Pulses

0x66

TSS463B Datasheet(PDF) 9 Page - ATMEL Corporation

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