CoreAHB

v2.1

3

CoreAHB Port List

Table 2 on page 4 lists the ports present on the AHB Bus component. Seven groups of signals can be identified.

1. Common AHB system signals (clock and reset)

2. Remap input

3. AHB mirrored master 0 (dummy master) related connections

4. Signals common to mirrored master interfaces 1 to 3

5. AHB mirrored master signals specific to each master

6. Signals common to all 16 AHB mirrored slave interfaces

7. AHB mirrored slave (master) signals specific to each slave

AHB mirrored master 1 interface

AHBmmaster1

Connection for lowest priority, default bus master

AHB mirrored master 2 interface

AHBmmaster2

Connection for middle priority bus master

AHB mirrored master 3 interface

AHBmmaster3

Connection for highest priority bus master

AHBmslave0

AHB mirrored slave 0 interface

Normally connected to AHBslave_base interface of Memory Controller

AHBmslave1

AHB mirrored slave 1 interface

AHBmslave2

AHB mirrored slave 2 interface

AHBmslave3

AHB mirrored slave 3 interface

AHBmslave4

AHB mirrored slave 4 interface

AHBmslave5

AHB mirrored slave 5 interface

AHBmslave6

AHB mirrored slave 6 interface

AHBmslave7

AHB mirrored slave 7 interface

AHBmslave8

AHB mirrored slave 8 interface

AHBmslave9

AHB mirrored slave 9 interface

AHBmslave10

AHB mirrored slave 10 interface

AHBmslave11

AHB mirrored slave 11 interface

AHBmslave12

AHB mirrored slave 12 interface

AHBmslave13

AHB mirrored slave 13 interface

AHBmslave14

AHB mirrored slave 14 interface

AHBmslave15

AHB mirrored slave 15 interface

Table 1 • CoreAHB Bus Connections (Continued)

Connection

CoreConsole

Label

Description