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EX128-CS100 Datasheet(PDF) 25 Page - Actel Corporation

Part # EX128-CS100
Description  eX Family FPGAs
PDF  49 Pages
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Manufacturer  ACTEL [Actel Corporation]
Direct Link  http://www.actel.com
Logo ACTEL - Actel Corporation

EX128-CS100 Datasheet(HTML) 25 Page - Actel Corporation

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eX Family FPGAs
v4.3
1-21
Timing Characteristics
Timing characteristics for eX devices fall into three
categories: family-dependent, device-dependent, and
design-dependent.
The
input
and
output
buffer
characteristics are common to all eX family members.
Internal routing delays are device-dependent. Design
dependency means actual delays are not determined
until after placement and routing of the user’s design are
complete. Delay values may then be determined by using
the Timer utility or performing simulation with post-
layout delays.
Critical Nets and Typical Nets
Propagation delays are expressed only for typical nets,
which are used for initial design performance evaluation.
Critical net delays can then be applied to the most timing
critical paths. Critical nets are determined by net
property assignment prior to placement and routing. Up
to six percent of the nets in a design may be designated
as critical.
Long Tracks
Some nets in the design use long tracks. Long tracks are
special routing resources that span multiple rows,
columns, or modules. Long tracks employ three to five
antifuse connections. This increases capacitance and
resistance, resulting in longer net delays for macros
connected to long tracks. Typically, no more than six
percent of nets in a fully utilized device require long
tracks. Long tracks contribute approximately 4 ns to
8.4 ns
delay.
This
additional
delay
is
represented
statistically in higher fanout routing delays.
Timing Derating
eX devices are manufactured with a CMOS process.
Therefore, device performance varies according to
temperature, voltage, and process changes. Minimum
timing parameters reflect maximum operating voltage,
minimum
operating
temperature,
and
best-case
processing.
Maximum
timing
parameters
reflect
minimum
operating
voltage,
maximum
operating
temperature, and worst-case processing.
Temperature and Voltage Derating Factors
Table 1-16 • Temperature and Voltage Derating Factors
(Normalized to Worst-Case Commercial, TJ = 70°C, VCCA = 2.3V)
VCCA
Junction Temperature (TJ)
–55
–40
0
25
70
85
125
2.3
0.79
0.80
0.87
0.88
1.00
1.04
1.13
2.5
0.74
0.74
0.81
0.83
0.93
0.97
1.06
2.7
0.69
0.70
0.76
0.78
0.88
0.91
1.00



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