EX128-CS100PP datasheet(28/49 Pages) ACTEL

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eX Family FPGAs

1- 24

v4.3

Table 1-19 • eX Family Timing Characteristics

(Worst-Case Commercial Conditions VCCA = 2.3V, VCCI = 2.3 V or 3.0V, TJ = 70°C)

‘–P’ Speed

‘Std’ Speed

‘–F’ Speed

Parameter

Description

Min.

Max.

Min.

Max.

Min.

Max.

Units

Dedicated (Hard-Wired) Array Clock Networks

tHCKH

Input LOW to HIGH

(Pad to R-Cell Input)

1.1

1.6

2.3

tHCKL

Input HIGH to LOW

(Pad to R-Cell Input)

1.1

1.6

2.3

tHPWH

Minimum Pulse Width HIGH

1.4

2.0

2.8

tHPWL

Minimum Pulse Width LOW

1.4

2.0

2.8

tHCKSW

Maximum Skew

<0.1

tHP

Minimum Period

2.8

4.0

5.6

fHMAX

Maximum Frequency

357

250

178

MHz

Routed Array Clock Networks

tRCKH

Input LOW to HIGH (Light Load)

(Pad to R-Cell Input) MAX.

1.0

1.4

2.0

tRCKL

Input HIGH to LOW (Light Load)

(Pad to R-Cell Input) MAX.

1.0

1.4

2.0

tRCKH

Input LOW to HIGH (50% Load)

(Pad to R-Cell Input) MAX.

1.2

1.7

2.4

tRCKL

Input HIGH to LOW (50% Load)

(Pad to R-Cell Input) MAX.

1.2

1.7

2.4

tRCKH

Input LOW to HIGH (100% Load)

(Pad to R-Cell Input) MAX.

1.4

2.0

2.8

tRCKL

Input HIGH to LOW (100% Load)

(Pad to R-Cell Input) MAX.

1.4

2.0

2.8

tRPWH

Min. Pulse Width HIGH

1.4

2.0

2.8

tRPWL

Min. Pulse Width LOW

1.4

2.0

2.8

tRCKSW*

Maximum Skew (Light Load)

0.2

0.3

0.4

tRCKSW*

Maximum Skew (50% Load)

0.2

0.3

tRCKSW*

Maximum Skew (100% Load)

0.1

0.2

Note: *Clock skew improves as the clock network becomes more heavily loaded.

EX128-CS100PP Datasheet(PDF) 28 Page - Actel Corporation

EX128-CS100PP Datasheet(HTML) 28 Page - Actel Corporation

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