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LTM4608

4608f

APPLICATIONS INFORMATION

Output Margining

For a convenient system stress test on the LTM4608’s

output, the user can program the LTM4608’s output to

±5%, ±10% or ±15% of its normal operational voltage.

The margin pin with a voltage divider is driven with a small

three-state gate as shown in Figure 18, for the three margin

states (high, low, no margin). When the MGN pin is low, it

forces negative margining in which the output voltage is

below the regulation point. When MGN is high, the output

voltage is forced to above the regulation point. The amount

of output voltage margining is determined by the BSEL

pin. When BSEL is low, it is 5%. When BSEL is high, it is

10%. When BSEL is ﬂoating, it is 15%. When margining

is active, the internal output overvoltage and undervoltage

comparators are disabled and PGOOD remains high. Mar-

gining is disabled by tying the MGN pin to VOUT.

Thermal Considerations and Output Current Derating

The power loss curves in Figures 7 and 8 can be used

in coordination with the load current derating curves in

Figures 9 to 16 for calculating an approximate θJA for the

module with various heat sinking methods. Thermal models

are derived from several temperature measurements at

the bench, and thermal modeling analysis. Thermal Ap-

plication Note 103 provides a detailed explanation of the

analysis for the thermal models and the derating curves.

Tables 4 and 5 provide a summary of the equivalent θJA

for the noted conditions. These equivalent θJA parameters

are correlated to the measured values and improve with

air ﬂow. The junction temperature is maintained at 125°C

or below for the derating curves.

Safety Considerations

The LTM4608 modules do not provide isolation from VIN to

VOUT. There is no internal fuse. If required, a slow blow fuse

with a rating twice the maximum input current needs to be

provided to protect each unit from catastrophic failure.

Layout Checklist/Example

The high integration of LTM4608 makes the PCB board

layout very simple and easy. However, to optimize its

electrical and thermal performance, some layout con-

siderations are still necessary.

• Use large PCB copper areas for high current path,

including VIN, GND and VOUT. It helps to minimize the

PCB conduction loss and thermal stress.

• Place high frequency ceramic input and output capaci-

tors next to the VIN, GND and VOUT pins to minimize

high frequency noise.

• Place a dedicated power ground layer underneath the

unit.

• To minimize the via conduction loss and reduce module

thermal stress, use multiple vias for interconnection

between top layer and other power layers.

• Do not put vias directly on the pads, unless they are

capped.

• Use a separated SGND ground copper area for com-

ponents connected to signal pins. Connect the SGND

to GND underneath the unit.

Figure 17 gives a good example of the recommended

layout.

Figure 17. Recommended PCB Layout

GND

4608 F17

CIN

COUT

CIN

VIN

VOUT

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