HC210W datasheet(11/228 Pages) ALTERA

11 / 228 page

Altera Corporation

2–3

September 2008

Preliminary

Functional Description

savings, which results in low-cost structured ASICs with

high-performance and low-power suitable for a wide variety of

applications.

The SRAM configuration cells of the Stratix II FPGAs are replaced in

HardCopy II devices with metal connections, which define the function

of logic, memory, phase-locked loop (PLL), and I/O elements (IOEs) in

the device. These resources are interconnected using metallization layers.

Once a HardCopy II device is manufactured, the functionality of the

device is fixed.

HardCopy II devices are manufactured using the same 90-nm process

technology and operate using the same core voltage (1.2 V) as Stratix II

FPGAs. Additionally, almost all architectural features in HardCopy II

devices are functionally equivalent to features found in the Stratix II

FPGA architecture. HardCopy II devices feature HCells, memory blocks,

PLLs, and IOEs (Figure 2–1).

Figure 2–1. Example Block Diagram of HC230 Device

Note (1)

Note to Figure 2–1:

(1)

Figure 2–1 shows a graphical representation of the device floor plan. A detailed floor plan is available in the

Quartus II software.

IOE

Fast

PLL

Enhanced

PLL

Fast

PLL

IOE

IOEs

M-RAM Block

IOE

Array

of HCells

Array

of HCells

Array

of HCells

Array

of HCells

Array

of HCells

Array

of HCells

M4K RAM Blocks

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