SN74ACT3638

512

× 32 × 2

CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SCAS228D – JUNE 1992 – REVISED APRIL 1998

15

POST OFFICE BOX 655303

th(D)

tw(CLKL)

tc

tsu(EN)

CLKA

ORB

W1

A0 – A31

MBA

ENA

CSA

W/RA

IRA

CLKB

CSB

W/RB

MBB

ENB

W1

B0 – B31

tc

th(EN)

tsu(EN)

th(EN)

tpd(C-OR)

tpd(C-OR)

Old Data in FIFO1 Output Register

Old Data in FIFO1 Output Register

ta

12

3

Low

High

tw(CLKL)

tw(CLKH)

th(EN)

tsu(EN)

tsu(D)

tsk1†

Low

High

Low

RDYB

tpd(C-R)

tpd(C-R)

tw(CLKH)

High

† tsk1 is the minimum time between a rising CLKA edge and a rising CLKB edge for ORB to transition high and to clock the next word to the FIFO1

output register in three CLKB cycles. If the time between the rising CLKA edge and rising CLKB edge is less than tsk1, then the transition of

ORB high and load of the first word to the output register may occur one CLKB cycle later than shown.

Figure 7. ORB-Flag Timing and First Data-Word Fall-Through When FIFO1 Is Empty