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SN74ACT3638PCB Datasheet(PDF) 27 Page - Texas Instruments

Part # SN74ACT3638PCB
Description  512 횞 32 횞 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
PDF  30 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

SN74ACT3638PCB Datasheet(HTML) 27 Page - Texas Instruments

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SN74ACT3638
512
× 32 × 2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS228D – JUNE 1992 – REVISED APRIL 1998
27
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, CL = 30 pF (see Figures 1 through 23)
PARAMETER
’ACT3638-15
’ACT3638-20
’ACT3638-30
UNIT
PARAMETER
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
fmax
66.7
50
33.4
MHz
ta
Access time, CLKA
↑ to A0–A31 and CLKB↑ to B0–B31
3
11
3
13
3
15
ns
tpd(C-IR)
Propagation delay time, CLKA
↑ to IRA and CLKB↑ to IRB
1
8
1
10
1
12
ns
tpd(C-OR)
Propagation delay time, CLKA
↑ to ORA and CLKB↑ to ORB
1
8
1
10
1
12
ns
tpd(C-R)
Propagation delay time, CLKA
↑ to RDYA and CLKB↑ to RDYB
1
8
1
10
1
12
ns
tpd(W-R)
Propagation delay time, W/RA to RDYA and W/RB to RDYB
1
8
1
10
1
12
ns
tpd(C-AE)
Propagation delay time, CLKA
↑ to AEA and CLKB↑ to AEB
1
8
1
10
1
12
ns
tpd(C-AF)
Propagation delay time, CLKA
↑ to AFA and CLKB↑ to AFB
1
8
1
10
1
12
ns
tpd(C-MF)
Propagation delay time, CLKA
↑ to MBF1 low or MBF2 high and
CLKB
↑ to MBF2 low or MBF1 high
0
8
0
10
0
12
ns
tpd(C-MR)
Propagation delay time, CLKA
↑ to B0–B31† and CLKB↑ to
A0 – A31‡
3
13.5
3
15
3
17
ns
tpd(M-DV)
Propagation delay time, MBA to A0 – A31 valid and MBB to
B0 – B31 valid
3
13
3
15
3
17
ns
tpd(R-F)
Propagation delay time, RST1 low to AEB low, AFA high, and
MBF1 high, and RST2 low to AEA low, AFB high, and MBF2
high
1
15
1
20
1
30
ns
ten
Enable time, CSA and W/RA low to A0 – A31 active and CSB
low and W/RB high to B0 – B31 active
2
12
2
13
2
14
ns
tdis
Disable time, CSA or W/RA high to A0 – A31 at high impedance
and CSB high or W/RB low to B0 – B31 at high impedance
1
13
1
14
1
15
ns
† Writing data to the mail1 register when the B0 – B31 outputs are active and MBB is high
‡ Writing data to the mail2 register when the A0 – A31 outputs are active and MBA is high



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