SN74ACT3638

512

× 32 × 2

CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SCAS228D – JUNE 1992 – REVISED APRIL 1998

26

POST OFFICE BOX 655303

timing requirements over recommended ranges of supply voltage and operating free-air

temperature (see Figures 1 through 23)

’ACT3638-15

’ACT3638-20

’ACT3638-30

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

UNIT

fclock

Clock frequency, CLKA or CLKB

66.7

50

33.4

MHz

tc

Clock cycle time, CLKA or CLKB

15

20

30

ns

tw(CLKH)

Pulse duration, CLKA and CLKB high

6

8

10

ns

tw(CLKL)

Pulse duration, CLKA and CLKB low

6

8

10

ns

tsu(D)

Setup time, A0 – A31 before CLKA

↑ and B0–B31 before CLKB↑

4.5

5

6

ns

tsu(EN)

Setup time, CSA, W/RA, ENA, and MBA before CLKA

↑; CSB,

W/RB, ENB, and MBB before CLKB

↑

5

6

7

ns

tsu(RM)

Setup time, RTM and RFM before CLKB

↑

6

6.5

7

ns

tsu(RS)

Setup time, RST1 or RST2 low before CLKA

↑ or CLKB↑†

5

6

7

ns

tsu(FS)

Setup time, FS0 and FS1 before RST1 and RST2 high

7

8

9

ns

th(D)

Hold time, A0 – A31 after CLKA

↑ and B0–B31 after CLKB↑

0

0

0

ns

th(EN)

Hold time, CSA, W/RA, ENA, and MBA after CLKA

↑; CSB, W/

RB, ENB, and MBB after CLKB

↑

0

0

0

ns

th(RM)

Hold time, RTM and RFM after CLKB

↑

0

0

0

ns

th(RS)

Hold time, RST1 or RST2 low after CLKA

↑ or CLKB↑†

4

4

5

ns

th(FS)

Hold time, FS0 and FS1 after RST1 and RST2 high

2

3

3

ns

tsk1‡

Skew time between CLKA

↑ and CLKB↑ for ORA, ORB, IRA, and

IRB

8

9

11

ns

tsk2‡

Skew time between CLKA

↑ and CLKB↑ for AEA, AEB, AFA, and

AFB

12

16

20

ns

† Requirement to count the clock edge as one of at least four needed to reset a FIFO

‡ Skew time is not a timing constraint for proper device operation and is included only to illustrate the timing relationship between CLKA cycle and

CLKB cycle.