TMS320UVC5402 datasheet(5/60 Pages) TI

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TMS320UVC5402

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS100A – APRIL 1999 – REVISED AUGUST 1999

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

terminal functions

The following table lists each signal, function, and operating mode(s) grouped by function.

Terminal Functions

TERMINAL

TYPE†

DESCRIPTION

TERMINAL

NAME

TYPE†

DESCRIPTION

DATA SIGNALS

A19

(MSB)

A18

A17

A16

A15

A14

A13

A12

A11

A10

(LSB)

O/Z

Parallel address bus A19 [most significant bit (MSB)] through A0 [least significant bit (LSB)]. The lower sixteen

address pins (A0 to A15) are multiplexed to address all external memory (program, data) or I/O, while the upper

four address pins (A16 to A19) are only used to address external program space. These pins are placed in the

high-impedance state when the hold mode is enabled, or when EMU1/OFF is low.

D15

(MSB)

D14

D13

D12

D11

D10

(LSB)

I/O/Z

Parallel data bus D15 (MSB) through D0 (LSB). The sixteen data pins (D0 to D15) are multiplexed to transfer

data between the core CPU and external data/program memory or I/O devices. The data bus is placed in the

high-impedance state when not outputting or when RS or HOLD is asserted. The data bus also goes into the

high-impedance state when EMU1/OFF is low.

The data bus has bus holders to reduce the static power dissipation caused by floating, unused pins. These bus

holders also eliminate the need for external bias resistors on unused pins. When the data bus is not being driven

by the ’UVC5402, the bus holders keep the pins at the previous logic level. The data bus holders on the

’UVC5402 are disabled at reset and can be enabled/disabled via the BH bit of the bank-switching control register

(BSCR).

INITIALIZATION, INTERRUPT, AND RESET OPERATIONS

IACK

O/Z

Interrupt acknowledge signal. IACK Indicates receipt of an interrupt and that the program counter is fetching the

interrupt vector location designated by A15–A0. IACK also goes into the high-impedance state when EMU1/OFF

is low.

INT0

INT1

INT2

INT3

External user interrupts. INT0–INT3 are prioritized and are maskable by the interrupt mask register (IMR) and

the interrupt mode bit. INT0 –INT3 can be polled and reset by way of the interrupt flag register (IFR).

NMI

Nonmaskable interrupt. NMI is an external interrupt that cannot be masked by way of the INTM or the IMR. When

NMI is activated, the processor traps to the appropriate vector location.

Reset. RS causes the digital signal processor (DSP) to terminate execution and causes a reinitialization of the

CPU and peripherals. When RS is brought to a high level, execution begins at location 0FF80h of program

memory. RS affects various registers and status bits.

† I = input, O = output, Z = high impedance, S = supply

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