TMS77C82 datasheet(49/59 Pages) TI

49 / 59 page

TMS370Cx7x

8-BIT MICROCONTROLLER

SPNS034C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

external clocking requirements for clock divided by 4† (see Figure 22)

NO.

PARAMETER

MIN

MAX

UNIT

tw(Cl)

Pulse duration, XTAL2/CLKIN (see Note 10)

tr(Cl)

Rise time, XTAL2/CLKIN

tf(CI)

Fall time, XTAL2/CLKIN

td(CIH-SCL)

Delay time, XTAL2/CLKIN rise to SYSCLK fall

100

CLKIN

Crystal operating frequency

MHz

SYSCLK

System clock‡

0.5

MHz

† For VIL and VIH, refer to recommended operating conditions.

‡ SYSCLK = CLKIN/4

NOTE 10: This pulse can be either a high pulse, which extends from the earliest valid high to the final valid high in an XTAL2/CLKIN cycle, or a

low pulse, which extends from the earliest valid low to the final valid low in an XTAL2/CLKIN cycle.

XTAL2/CLKIN

SYSCLK

Figure 22. External Clock Timing for Divide-by-4

external clocking requirements for clock divided by 1 (PLL)† (see Figure 23)

NO.

PARAMETER

MIN

MAX

UNIT

tw(Cl)

Pulse duration, XTAL2/CLKIN (see Note 10)

tr(Cl)

Rise time, XTAL2/CLKIN

tf(CI)

Fall time, XTAL2/CLKIN

td(CIH-SCH)

Delay time, XTAL2/CLKIN rise to SYSCLK rise

100

CLKIN

Crystal operating frequency

MHz

SYSCLK

System clock§

MHz

† For VIL and VIH, refer to recommended operating conditions.

§ SYSCLK = CLKIN/1

NOTE 10: This pulse can be either a high pulse, which extends from the earliest valid high to the final valid high in an XTAL2/CLKIN cycle, or a

low pulse, which extends from the earliest valid low to the final valid low in an XTAL2/CLKIN cycle.

XTAL2/CLKIN

SYSCLK

Figure 23. External Clock Timing for Divide-by-1

TMS77C82 Datasheet(PDF) 49 Page - Texas Instruments

TMS77C82 Datasheet(HTML) 49 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59

Datasheet Download

Link URL