TMS77C82 datasheet(26/59 Pages) TI

26 / 59 page

TMS370Cx7x

8-BIT MICROCONTROLLER

SPNS034C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

timer 1 (T1) module (continued)

The TMS370Cx7x device includes a 24-bit watchdog (WD) timer, contained in the T1 module, which can be

software programmed as an event counter, pulse accumulator, or interval timer if the WD function is not used.

The WD function is to monitor software and hardware operation, and it implements a system reset when the

WD counter is not serviced properly (WD counter overflow or WD counter is reinitialized by an incorrect value).

The WD can be configured as one of the three mask options: standard WD, hard WD, or simple counter.

D Standard watchdog configuration for EPROM and mask-ROM devices (see Figure 8)

–

Watchdog

–

Ten different WD overflow rates ranging from 6.55 ms to 3.35 s at 5-MHz SYSCLK

–

A WD reset key (WDRST) register is used to clear the watchdog counter (WDCNTR) when a correct

value is written.

–

Generates a system reset if an incorrect value is written to the WD reset key or if the counter

overflows

–

A WD overflow flag (WD OVRFL INT FLAG) bit that indicates whether the WD timer initiated a

system reset

–

Non-watchdog

–

Watchdog timer can be configured as an event counter, pulse accumulator, or an interval timer

16-Bit

Watchdog Counter

Reset

Prescaler

Clock

Watchdog Reset Key

WD OVRFL

TAP SEL

WD OVRFL

RST ENA

System Reset

T1CTL1.7

WDRST.7-0

WDCNTR.15-0

T1CTL2.7

T1CTL2.5

WD OVRFL

INT ENA

Interrupt

T1CTL2.6

WD OVRFL

INT FLAG

Figure 8. Standard Watchdog

TMS77C82 Datasheet(PDF) 26 Page - Texas Instruments

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