TMS77C82 datasheet(10/59 Pages) TI

10 / 59 page

TMS370Cx7x

8-BIT MICROCONTROLLER

SPNS034C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

memory map (continued)

Interrupts and Reset

Vectors; Trap Vectors

Peripheral File Control Registers

1000h–100Fh

Reserved†

1F00h

24K-Byte ROM

(2000h–7FFFh)

256-Byte Data EEPROM

(1F00h–1FFFh)

Peripheral File

512-Byte RAM

(0000h–01FFh)

0000h

10C0h

1100h

2000h

7FC0h

8000h

FFFFh

Reserved†

0200h

1000h

Reserved†

1010h–101Fh

System Control

1020h–102Fh

Digital Port Control

1030h–103Fh

Reserved†

Not Available‡

1040h–104Fh

Timer 1 Peripheral Contr.

1050h–105Fh

Reserved†

1060h–106Fh

Timer 2A Peripheral Contr.

1070h–107Fh

ADC1 Peripheral Contr.

1080h–10BFh

Reserved†

Vectors

7FC0h–7FDFh

Trap 15 – 0

7FE0h–7FEBh

Reserved†

7FECh–7FEDh

ADC1

7FEEh–7FEFh

Timer 2A

7FF0h–7FF1h

Reserved†

7FF2h–7FF3h

Reserved†

7FF4h–7FF5h

Timer 1

7FF6h–7FF7h

Reserved†

7FF8h–7FF9h

Interrupt 3

7FFAh–7FFBh

Interrupt 2

7FFCh–7FFDh

Interrupt 1

7FFEh–7FFFh

Reset

Reserved†

† Reserved = the address space is reserved for future expansion.

‡ Not available = address space is unavailable in the mode illustrated.

Figure 3. TMS370Cx7x Memory Map

RAM / register file (RF)

Locations within RAM address space can serve as either register file or general-purpose read/write memory,

program memory, or stack instructions. The TMS370Cx7x device contains 512 bytes of internal RAM mapped

beginning at location 0000h and continuing through location 01FFh which is shown in Figure 3. The first

256 bytes of RAM (0000h – 00FFh) are the register files, R0 through R255.

The first two registers, R0 and R1, are also called registers A and B, respectively. Some instructions implicitly

use register A or B; for example, the instruction LDSP (load SP) assumes that the value to be loaded into the

stack pointer is contained in register B. Registers A and B are the only registers cleared on reset.

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