September 2006

PCS2I99447

rev 0.4

3.3V/2.5V 1:9 LVCMOS Clock Fanout Buffer

7 of 14

Notice: The information in this document is subject to change without notice.

round trip delay (in this case 4.0ns). Since this step is

well above the threshold region it will not cause any false

clock

triggering;

however,

designers

may

be

uncomfortable with unwanted reflections on the line. To

better match the impedances when driving multiple lines,

the situation in Figure 4 “Optimized Dual Line

Termination” should be used. In this case, the series

terminating resistors are reduced such that when the

parallel combination is added to the output buffer

impedance the line impedance is perfectly matched.

17

Ω + 16Ω ║ 16Ω = 50Ω ║ 50Ω

25

Ω = 25Ω

Figure 4. Optimized Dual Line Termination

The Following Figures Illustrate the Measurement Reference for the PCS2I99447 Clock Driver Circuit

Figure 5. CCLK PCS2I99447 AC Test Reference for Vcc = 3.3V and Vcc = 2.5V

PCS2I99447

OUTPUT BUFFER

17Ω

PCS2I99447

Pulse

Generator

Z=50

Ω

TT