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LPC2921 Datasheet(PDF) 58 Page - NXP Semiconductors

Part # LPC2921
Description  ARM9 microcontroller with CAN, LIN, and USB
PDF  83 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

LPC2921 Datasheet(HTML) 58 Page - NXP Semiconductors

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LPC2921_23_25_1
© NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 01 — 15 June 2009
58 of 83
NXP Semiconductors
LPC2921/2923/2925
ARM9 microcontroller with CAN, LIN, and USB
[1]
Conditions: VSS(IO) =0V, VDDA(ADC3V3) = 3.3 V.
[2]
The ADC is monotonic, there are no missing codes.
[3]
The differential linearity error (ED) is the difference between the actual step width and the ideal step width. See Figure 14.
[4]
The integral non-linearity (EL(adj)) is the peak difference between the center of the steps of the actual and the ideal transfer curve after
appropriate adjustment of gain and offset errors. See Figure 14.
[5]
The offset error (EO) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the
ideal curve. See Figure 14.
[6]
The gain error (EG) is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset
error, and the straight line which fits the ideal transfer curve. See Figure 14.
[7]
The absolute error (ET) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated ADC
and the ideal transfer curve. See Figure 14.
[8]
See Figure 13.
Table 32.
ADC static characteristics
VDDA(ADC3V3) = 3.0 V to 3.6 V; Tamb = −40 °C to +85 °C unless otherwise specified; ADC frequency 4.5 MHz.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VVREFN
voltage on pin VREFN
0
-
VVREFP − 2V
VVREFP
voltage on pin VREFP
VVREFN +2 -
VDDA(ADC3V3)
V
VIA
analog input voltage
VVREFN
-VVREFP
V
Zi
input impedance
between VVREFN and
VVREFP
4.4
-
-
k
Ω
Cia
analog input capacitance
-
-
1
pF
ED
differential linearity error
[1][2][3] --
±1
LSB
EL(adj)
integral non-linearity
[1][4] --
±2
LSB
EO
offset error
[1][5] --
±3
LSB
EG
gain error
[1][6] --
±0.5
%
ET
absolute error
[1][7] --
±4
LSB
Rvsi
voltage source interface
resistance
[8] -
-
40
k
Ω
FSR
full scale range
2
-
10
bit
Fig 13. Suggested ADC interface - LPC2921/2923/2925 ADC1/2 IN[y] pin
LPC2XXX
ADC IN[y]SAMPLE
ADC IN[y]
20 k
Ω
3 pF
5 pF
Rvsi
VSS(IO), VSS(CORE)
VEXT
002aae280



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