PCF8579TSLASH1 datasheet(7/41 Pages) NXP

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PCF8579_5

Product data sheet

Rev. 05 — 11 May 2009

7 of 41

NXP Semiconductors

PCF8579

LCD column driver for dot matrix graphic displays

7.2 Pin description

[1]

The TEST pin must be connected to VSS.

[2]

Do not connect, these pins are reserved.

Functional description

The PCF8579 column driver is designed for use with the PCF8578. Together they form a

general purpose LCD dot matrix chip set.

Typically up to 16 PCF8579s may be used with one PCF8578 (examples of cascading the

devices see Table 16, Figure 21, Figure 22, Figure 23 and Figure 24). Each of the

PCF8579s is identiﬁed by a unique 4-bit hardware subaddress, set by pins A0 to A3.

The PCF8578 can operate with up to 32 PCF8579s when using two I2C-bus slave

addresses. The two slave addresses are set by the logic level on input SA0.

8.1 Power-on reset

At power-on the PCF8579 resets to a deﬁned starting condition as follows:

1. Display blank (in conjunction with PCF8578)

2. 1:32 multiplex rate

3. Start bank 0 selected

4. Data pointer is set to X, Y address 0, 0

5. Character mode

6. Subaddress counter is set to 0

7. I2C-bus interface is initialized

Table 3.

Pin description

Symbol

Description

VSO56

LQFP64,

TQFP64

SDA

I2C-bus serial data input/output

SCL

I2C-bus serial clock input

SYNC

cascade synchronization output

CLK

external clock input/output

VSS

ground

TEST[1]

test pin

SA0

I2C-bus slave address input (bit 0)

A3 to A0

8 to 11

14, 16 to 18

I2C-bus subaddress inputs

VDD

supply voltage

n.c.[2]

15, 19, 21, 25

to 29, 34

not connected

V3, V4

14, 15

22, 23

LCD bias voltage inputs

VLCD

LCD supply voltage

C39 to C0

17 to 56

30 to 33, 35

to 64, 1 to 6

LCD column driver outputs

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