PCF8579TSLASH1 datasheet(13/41 Pages) NXP

13 / 41 page

PCF8579_5

Product data sheet

Rev. 05 — 11 May 2009

13 of 41

NXP Semiconductors

PCF8579

LCD column driver for dot matrix graphic displays

8.4 Timing generator

The timing generator of the PCF8579 organizes the internal data ﬂow from the RAM to the

display drivers. An external synchronization pulse SYNC is received from the PCF8578.

This signal maintains the correct timing relationship between cascaded devices.

8.5 Column drivers

Outputs C0 to C39 are column drivers which must be connected to the LCD. Unused

outputs should be left open-circuit.

8.6 Characteristics of the I2C-bus

The I2C-bus is for bidirectional, two-line communication between different ICs or modules.

The two lines are a Serial Data Line (SDA) and a Serial Clock Line (SCL) which must be

connected to a positive supply via a pull-up resistor. Data transfer may be initiated only

when the bus is not busy.

8.6.1 Bit transfer

One data bit is transferred during each clock pulse. The data on the SDA line must remain

stable during the HIGH period of the clock pulse as changes in the data line at this

moment will be interpreted as control signals.

8.6.2 START and STOP conditions

Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW

transition of the data line, while the clock is HIGH, is deﬁned as the START condition (S).

A LOW-to-HIGH transition of the data line while the clock is HIGH, is deﬁned as the STOP

condition (P).

8.6.3 System conﬁguration

A device transmitting a message is a transmitter, a device receiving a message is the

receiver. The device that controls the message ﬂow is the master and the devices which

are controlled by the master are the slaves.

8.6.4 Acknowledge

The number of data bytes transferred between the START and STOP conditions from

transmitter to receiver is unlimited. Each data byte of eight bits is followed by one

acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter,

whereas the master generates an extra acknowledge related clock pulse. A slave receiver

which is addressed must generate an acknowledge after the reception of each byte. Also

a master must generate an acknowledge after the reception of each byte that has been

clocked out of the slave transmitter. The device that acknowledges must pull down the

SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during

the HIGH period of the acknowledge related clock pulse (set-up and hold times must be

taken into consideration). A master receiver must signal the end of a data transmission to

the transmitter by not generating an acknowledge on the last byte that has been clocked

out of the slave. In this event the transmitter must leave the data line HIGH to enable the

master to generate a STOP condition.

PCF8579T/1 Datasheet(PDF) 13 Page - NXP Semiconductors

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