LTC3577 datasheet(45/52 Pages) LINER

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LTC3577/LTC3577-1

3577f

OPERATION

Power-Down via Pushbutton Timing

The timing diagram, Figure 22, shows the LTC3577

powering down by μC/μP control. For this example the

pushbutton circuitry starts in the PON state with a bat-

tery connected and all bucks enabled. In this case the

pushbutton is applied (ON low) for at least 50ms, which

generates a low impedance on the PBSTAT output. After

receiving the PBSTAT the μC/μP will drive the PWR_ON

input low. 50ms after PWR_ON goes low the WAKE

output will go low and the pushbutton circuitry will enter

the PDN2 state. The bucks are disabled together at once

upon entering the PDN2 state. Once entering the PDN2

state a 1 second wait time is initiated before entering the

POFF state. During this 1 second time ON and PWR_ON

inputs as well as external power application are ignored

to allow all LTC3577 generated supplies to go low. Though

the above assumes a battery present, the same operation

would take place with a valid external supply (VBUS or

WALL) with or without a battery present.

Upon entering the PDN2 state the LDOs and LED backlight

I2C registers are cleared effectively disabling both. If this

is not desirable the LDOs and LED backlight should be

disabled via I2C prior to entering the PDN2 state.

Holding ON low through the 1 second power-down period

will not cause a power-up event at end of the 1 second

period. The ON input must be brought high following the

power-down event and then go low again to establish a

valid power-up event.

UVLO Minimum Off-Time Timing (Low Battery)

The timing diagram, Figure 23, assumes the battery is either

missing or at a voltage below the VOUT UVLO threshold

and the application is running via external power (VBUS

or WALL). A glitch on the external supply causes VOUT

to drop below the VOUT UVLO threshold temporarily. The

VOUT UVLO condition will cause the pushbutton circuitry

to transition from the PON state to the PDN2 state. Upon

entering the PDN2 state WAKE and PG_DCDC will go low

while the bucks, LDOs and LED backlight power down

together. If the external supply recovers after entering the

PND2 state such that VOUT is no longer in UVLO then the

LTC3577 will transition back into the PUP2 state once the

PDN2 one second delay is complete. Though not shown

in Figure 23, the pushbutton logic brieﬂy visits the POFF

state when transitioning between PDN2 and PUP2. Enter-

ing the PUP2 state will cause the bucks to sequence up as

described previously in the power-up sections. The LDOs

and LED backlight must be re-enabled via I2C once device

is powered back up.

PBSTAT

PWR_ON

WAKE

BUCKS

PG_DCDC

STATE PON

PDN2

PUP2

PON

VBUS/WALL

BAT

ON (PB)

3577 F23

1SEC

BUCKS SEQUENCE UP

1 2 3

230ms

5SEC

Figure 23. UVLO Minimum Off-Time

Figure 22. Power-Down va Pushbutton Timing

PBSTAT

PWR_ON

WAKE

BUCK1-3

PG_DCDC

STATE

PON

PDN2

POFF

VBUS/WALL

BAT

ON (PB)

3577 F22

1SEC

50ms

μC/μP CONTROL

50ms

ALL BUCKS LOW

LTC3577 Datasheet(PDF) 45 Page - Linear Technology

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