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LTM9003 Datasheet(PDF) 1 Page - Linear Technology

Part # LTM9003
Description  12-Bit Digital Pre-Distortion Receiver Subsystem
PDF  24 Pages
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Manufacturer  LINER [Linear Technology]
Direct Link  http://www.linear.com
Logo LINER - Linear Technology

LTM9003 Datasheet(HTML) 1 Page - Linear Technology

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LTM9003
1
9003p
TYPICAL APPLICATION
DESCRIPTION
12-Bit Digital Pre-Distortion
Receiver Subsystem
The LTM®9003 is a 12-bit digital pre-distortion receiver
subsystem for the transmit path of cellular basestations.
Utilizing an integrated system in a package (SiP) tech-nol-
ogy, it includes a downconverting mixer, wideband filter
and analog-to-digital converter (ADC). The system is tuned
for an intermediate frequency (IF) of 184MHz and a signal
bandwidth of up to 125MHz. The 12-bit ADC samples at
rates up to 250Msps. Contact Linear Technology regard-
ing customization.
The high signal level downconverting active mixer is opti-
mized for high linearity, wide dynamic range IF sampling
applications. It includes a differential LO buffer amplifier
driving a double-balanced mixer. Broadband, integrated
transformers on the RF and LO inputs provide single
ended 50Ω interfaces. The RF and LO inputs are internally
matched to 50Ω from 1.1GHz to 1.8GHz.
The CLK input controls converter operation and may be
driven differentially or single-ended. An optional clock duty
cycle stabilizer allows high performance at full speed for
a wide range of clock duty cycles.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
Protected by U.S. Patents including 5481178, 6580258, 6304066, 6127815, 6498466, 6611131.
FFT of 4-Channel WCDMA Input at 1.95GHz
FEATURES
APPLICATIONS
n Fully Integrated Receiver Subsystem for Digital
Pre-Distortion Applications
n Down-Converting Mixer with Wide RF Frequency
Range: 400MHz to 3.8GHz
n 125MHz Wide Bandpass Filter, <0.5dB Passband
Ripple
n Low Power ADC with Up to 12-Bit Resolution,
250Msps Sample Rate
n –145.5dBm/Hz Input Noise Floor, 25.8dBm IIP3
n 1.5W Total Power Consumption
n 50Ω Single-Ended RF and LO Ports
n Internal Bypass Capacitance, No External
Components
n ADC Clock Duty Cycle Stabilizer
n 11.25mm
× 15mm LGA package
n Transmit ObservationPath Receivers
n Digital Pre-Distortion (DPD) Receivers
n Wideband Receiver
n Wideband Instrumentation
IF FREQUENCY (MHz)
154
–110
–90
–100
–80
–50
–60
–70
164
174
194
184
204
214
9003 TA01b
–40
LTM9003
OVDD = 2.5V
DGND
ENC–
ENC+
GND
LO
3.3V
2.5V
RF
9003 TA01
PA
D11
•
•
•
D0
LVDS
Electrical Specifications Subject to Change


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