ADCLK854SLASHPCBZ datasheet(1/16 Pages) AD

Part #	ADCLK854/PCBZ

Description	1.8 V, 12-LVDS/24-CMOS Output, Low Power Clock Fanout Buffer

PDF	16 Pages

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Manufacturer	AD [Analog Devices]

Direct Link	http://www.analog.com

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1.8 V, 12-LVDS/24-CMOS Output,

Low Power Clock Fanout Buffer

ADCLK854

Rev. 0

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rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.

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Tel: 781.329.4700

www.analog.com

Fax: 781.461.3113

FEATURES

2 selectable differential inputs

Selectable LVDS/CMOS outputs

Up to 12 LVDS (1.2 GHz) or 24 CMOS (250 MHz) outputs

<12 mW per channel (100 MHz operation)

54 fs rms integrated jitter (12 kHz to 20 MHz)

100 fs rms additive broadband jitter

2.0 ns propagation delay (LVDS)

135 ps output rise/fall (LVDS)

70 ps output-to-output skew (LVDS)

Sleep mode

Pin programmable control

1.8 V power supply

APPLICATIONS

Low jitter clock distribution

Clock and data signal restoration

Level translation

Wireless communications

Wired communications

Medical and industrial imaging

ATE and high performance instrumentation

GENERAL DESCRIPTION

The ADCLK854 is a 1.2 GHz/250 MHz LVDS/CMOS fanout

buffer optimized for low jitter and low power operation. Possible

configurations range from 12 LVDS to 24 CMOS outputs,

including combinations of LVDS and CMOS outputs. Three

control lines are used to determine whether fixed blocks of

outputs (three banks of four) are LVDS or CMOS outputs.

The ADCLK854 offers two selectable inputs and a sleep mode

feature. The IN_SEL pin state determines which input is fanned

out to all the outputs. The SLEEP pin enables a sleep mode to

power down the device.

The inputs accept various types of single-ended and differential

logic levels including LVPECL, LVDS, HSTL, CML, and CMOS.

Table 8 provides interface options for each type of connection.

This device is available in a 48-pin LFCSP package. It is specified

for operation over the standard industrial temperature range of

−40°C to +85°C.

FUNCTIONAL BLOCK DIAGRAM

OUT0 (OUT0A)

OUT0 (OUT0B)

OUT1 (OUT1A)

OUT1 (OUT1B)

OUT2 (OUT2A)

OUT2 (OUT2B)

OUT3 (OUT3A)

OUT3 (OUT3B)

LVDS/

CMOS

OUT4 (OUT4A)

OUT4 (OUT4B)

OUT5 (OUT5A)

OUT5 (OUT5B)

OUT6 (OUT6A)

OUT6 (OUT6B)

OUT7 (OUT7A)

OUT7 (OUT7B)

LVDS/

CMOS

OUT8 (OUT8A)

OUT8 (OUT8B)

OUT9 (OUT9A)

OUT9 (OUT9B)

OUT10 (OUT10A)

OUT10 (OUT10B)

OUT11 (OUT11A)

OUT11 (OUT11B)

LVDS/

CMOS

CTRL_C

CTRL_B

CTRL_A

IN_SEL

SLEEP

CLK1

CLK0

ADCLK854

VREF

VS/2

Figure 1.

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ADCLK854/PCBZ Datasheet(PDF) 1 Page - Analog Devices

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