ADCLK854

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still meet receiver input requirements in some applications. This

can be useful when driving long trace lengths on less critical

networks.

CMOS

CMOS

10Ω

50Ω

100Ω

100Ω

Figure 27. CMOS Output with Far End Termination

Because of the limitations of single-ended CMOS clocking,

consider using differential outputs when driving high speed

signals over long traces. The ADCLK854 offers LVDS outputs

that are better suited for driving long traces wherein the inherent

noise immunity of differential signaling provides superior

performance for clocking converters.

INPUT TERMINATION OPTIONS

For single-ended operation always bypass unused input to

GND, as shown in Figure 31.

input offset is with external resistor values; for example, using a

1.8 V CMOS with long traces to provide far end termination.

100Ω

CLK

CLK

100Ω

CLK

CLK

Figure 28. Typical AC-Coupled or DC-Coupled LVDS or HSTL Configuration

(See Table 8 for More Information)

CLK

CLK

CLK

CLK

Figure 29. Typical AC-Coupled or DC-Coupled CML Configuration

(See Table 8 for CML Coupling Limitations)

CLK

CLK

50Ω

50Ω

CLK

CLK

50Ω

50Ω

Figure 30. Typical AC-Coupled or DC-Coupled PECL Configuration

(See Table 8 for LVPECL DC-Coupling Limitations)

CLK

CLK

CLK

CLK

CLK

CLK

Figure 31. Typical 1.8 V CMOS Configurations for Short Trace Lengths

(See Table 8 for CMOS Compatibility)

CLK

CLK