XRT86VL30 datasheet(2/62 Pages) EXAR

2 / 62 page

XRT86VL30

T1/E1/J1 BITS ELEMENT - HARDWARE MANUAL

REV. 1.0.3

APPLICATIONS

• BITS Timing

• High-Density T1/E1/J1 interfaces for Multiplexers, Switches, LAN Routers and Digital Modems

• SONET/SDH terminal or Add/Drop multiplexers (ADMs)

• T1/E1/J1 add/drop multiplexers (MUX)

• Channel Service Units (CSUs): T1/E1/J1 and Fractional T1/E1/J1

• Digital Access Cross-connect System (DACs)

• Digital Cross-connect Systems (DCS)

• Frame Relay Switches and Access Devices (FRADS)

• ISDN Primary Rate Interfaces (PRA)

• PBXs and PCM channel bank

• T3 channelized access concentrators and M13 MUX

• Wireless base stations

• ATM equipment with integrated DS1 interfaces

• Multichannel DS1 Test Equipment

• T1/E1/J1 Performance Monitoring

• Voice over packet gateways

• Routers

FEATURES

• Supports Section 13 - Synchronization Interface in ITU G.703 for both Transmit and Receive Paths

• Supports SSM Synchronous Messaging Generation (BOC for T1, National Bits for E1) on the Transmit Path

• Supports SSM Synchronous Messaging Extraction (BOC for T1, National Bits for E1) on the Receive Path

• Supports BITS timing generation on the Transmit Outputs

• Supports BITS timing extraction from NRZ data on the Analog Receive Path

• Parallel Microcontroller Interface

• Independent, full duplex DS1 Tx and Rx Framer/LIUs

• Two 512-bit (two-frame) elastic store, PCM frame slip buffers (FIFO) on TX and Rx provide up to 8.192 MHz

asynchronous back plane connections with jitter and wander attenuation

• Supports input PCM and signaling data at 1.544, 2.048, 4.096 and 8.192 Mbits. Also supports 2-channel

multiplexed 12.352/16.384 (HMVIP/H.100) Mbit/s on the back plane bus

• Programmable output clocks for Fractional T1/E1/J1

• Supports Channel Associated Signaling (CAS)

• Supports Common Channel Signalling (CCS)

• Supports ISDN Primary Rate Interface (ISDN PRI) signaling

• Extracts and inserts robbed bit signaling (RBS)

• 3 Integrated HDLC controllers for transmit and receive, each controller having two 96-byte buffers (buffer 0 /

buffer 1)

• HDLC Controllers Support SS7

XRT86VL30 Datasheet(PDF) 2 Page - Exar Corporation