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STM32F101V8 Datasheet(PDF) 77 Page - STMicroelectronics

Part # STM32F101V8
Description  Medium-density access line, ARM-based 32-bit MCU with 64 or 128 KB Flash, 6 timers, ADC and 7 communication interfaces
PDF  81 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32F101V8 Datasheet(HTML) 77 Page - STMicroelectronics

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STM32F101x8, STM32F101xB
Revision history
Doc ID 13586 Rev 12
77/81
22-Nov-2007
4
Document status promoted from preliminary data to datasheet. Small text
changes.
STM32F101CB part number corrected in Table 1: Device summary.
Number of communication peripherals corrected for STM32F101Tx in
Table 2: Device features and peripheral counts (STM32F101xx medium-
density access line) and Number of GPIOs corrected for LQFP package.
Power supply schemes on page 13 modified.
Main function and default alternate function modified for PC14 and PC15
in Table 4: Medium-density STM32F101xx pin definitions, Note 6 added,
Remap column added.
Figure 10: Power supply scheme modified. VDD VSS ratings modified
and Note 1 modified in Table 5: Voltage characteristics. Note 1 modified
in Table 6: Current characteristics.
Note 2 added in Table 10: Embedded reset and power control block
characteristics.
48 and 72 MHz frequencies removed from Table 12, Table 13 and
Table 14. MCU ‘s operating conditions modified in Typical current
consumption on page 40.
IDD_VBAT typical value at 2.4 V modified and IDD_VBAT maximum value
added in Table 15: Typical and maximum current consumptions in Stop
and Standby modes. Note added in Table 16 on page 40 and Table 17 on
page 41. Table 18: Peripheral current consumption modified.
Figure 16: Typical current consumption in Stop mode with regulator in
Low-power mode versus temperature at VDD = 3.3 V and 3.6 V added.
Note removed below Figure 25: SPI timing diagram - slave mode and
CPHA = 0. Note added below Figure 26: SPI timing diagram - slave
mode and CPHA = 1(1).
Figure 29: Typical connection diagram using the ADC modified.
tSU(HSE) and tSU(LSE) conditions modified in Table 21 and Table 22,
respectively. Maximum values removed from Table 25: Low-power mode
wakeup timings. tRET conditions modified in Table 28: Flash memory
endurance and data retention. Conditions modified in Table 29: EMS
characteristics.
Impedance size specified in A.4: Voltage glitch on ADC input 0 on
page 71. Small text changes in Table 34: Output voltage characteristics.
Section 5.3.11: Absolute maximum ratings (electrical sensitivity)
updated.
Details on unused pins removed from General input/output
characteristics on page 52.
Table 40: SPI characteristics updated. Notes added and Ilkg removed in
Table 41: ADC characteristics. Note added in Table 42 and Table 45.
Note 3 and Note 2 added below Table 43: ADC accuracy - limited test
conditions. Avg_Slope and V25 modified in Table 45: TS characteristics.
JAvalue for VFQFPN36 package added in Table 50: Package thermal
characteristics
I2C interface characteristics on page 56 modified.
Order codes replaced by Section 7: Ordering information scheme.
Table 52.
Document revision history (continued)
Date
Revision
Changes



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