ATtiny261A datasheet(88/292 Pages) ATMEL

88 / 292 page

8197A–AVR–10/09

ATtiny261A/461A/861A

For actual placement of the I/O pins, refer to “Pinout ATtiny261A/461A/861A” on page 2. The

device-specific I/O register and bit locations are listed in the “Register Description” on page 110.

12.2.1

Speed

The maximum speed of the Timer/Counter1 is 64 MHz. However, if a supply voltage below 2.7

volts is used, it is recommended to use the Low Speed Mode (LSM), because the

Timer/Counter1 is not running fast enough on low voltage levels. In the Low Speed Mode the

fast peripheral clock is scaled down to 32 MHz. For more details about the Low Speed Mode,

see “PLLCSR – PLL Control and Status Register” on page 118.

12.2.2

Accuracy

The Timer/Counter1 is a 10-bit Timer/Counter module that can alternatively be used as an 8-bit

Timer/Counter. The Timer/Counter1 registers are basically 8-bit registers, but on top of that

there is a 2-bit High Byte Register (TC1H) that can be used as a common temporary buffer to

access the two MSBs of the 10-bit Timer/Counter1 registers by the AVR CPU via the 8-bit data

bus, if the 10-bit accuracy is used. Whereas, if the two MSBs of the 10-bit registers are written to

zero the Timer/Counter1 is working as an 8-bit Timer/Counter. When reading the low byte of any

8-bit register the two MSBs are written to the TC1H register, and when writing the low byte of

any 8-bit register the two MSBs are written from the TC1H register. Special procedures must be

followed when accessing the 10-bit Timer/Counter1 values via the 8-bit data bus. These proce-

dures are described in the section “Accessing 10-Bit Registers” on page 106.

12.2.3

Registers

The Timer/Counter (TCNT1) and Output Compare Registers (OCR1A, OCR1B, OCR1C and

OCR1D) are 8-bit registers that are used as a data source to be compared with the TCNT1 con-

tents. The OCR1A, OCR1B and OCR1D registers determine the action on the OC1A, OC1B and

OC1D pins and they can also generate the compare match interrupts. The OCR1C holds the

Timer/Counter TOP value, i.e. the clear on compare match value. The Timer/Counter1 High

Byte Register (TC1H) is a 2-bit register that is used as a common temporary buffer to access the

MSB bits of the Timer/Counter1 registers, if the 10-bit accuracy is used.

Interrupt request (overflow TOV1, and compare matches OCF1A, OCF1B, OCF1D and fault pro-

tection FPF1) signals are visible in the Timer Interrupt Flag Register (TIFR) and Timer/Counter1

Control Register D (TCCR1D). The interrupts are individually masked with the Timer Interrupt

Mask Register (TIMSK) and the FPIE1 bit in the Timer/Counter1 Control Register D (TCCR1D).

Control signals are found in the Timer/Counter Control Registers TCCR1A, TCCR1B, TCCR1C,

TCCR1D and TCCR1E.

12.2.4

Synchronization

In asynchronous clocking mode the Timer/Counter1 and the prescaler allow running the CPU

from any clock source while the prescaler is operating on the fast peripheral clock (PCK) having

frequency of 64 MHz (or 32 MHz in Low Speed Mode). This is possible because there is a syn-

chronization boundary between the CPU clock domain and the fast peripheral clock domain.

Figure 12-2 shows Timer/Counter 1 synchronization register block diagram and describes syn-

chronization delays in between registers. Note that all clock gating details are not shown in the

figure.

The Timer/Counter1 register values go through the internal synchronization registers, which

cause the input synchronization delay, before affecting the counter operation. The registers

TCCR1A, TCCR1B, TCCR1C, TCCR1D, OCR1A, OCR1B, OCR1C and OCR1D can be read

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