ATtiny261A datasheet(191/292 Pages) ATMEL

191 / 292 page

191

8197A–AVR–10/09

ATtiny261A/461A/861A

Figure 19-7. Parallel Programming Timing, Reading Sequence (within the Same Page) with Timing Requirements

Note:

The timing requirements shown in Figure 19-5 (i.e., tDVXH, tXHXL, and tXLDX) also apply to reading operation.

XTAL1

ADDR0 (Low Byte)

DATA (Low Byte)

DATA (High Byte)

ADDR1 (Low Byte)

DATA

PAGEL/BS1

XA0

XA1/BS2

LOAD ADDRESS

(LOW BYTE)

READ DATA

(LOW BYTE)

READ DATA

(HIGH BYTE)

LOAD ADDRESS

(LOW BYTE)

BVDV

OLDV

XLOL

OHDZ

Table 19-9.

Parallel Programming Characteristics, VCC = 5V ± 10%

Symbol

Parameter

Min

Typ

Max

Units

VPP

Programming Enable Voltage

11.5

12.5

IPP

Programming Enable Current

250

μA

tDVXH

Data and Control Valid before XTAL1 High

tXLXH

XTAL1 Low to XTAL1 High

200

tXHXL

XTAL1 Pulse Width High

150

tXLDX

Data and Control Hold after XTAL1 Low

tXLWL

XTAL1 Low to WR Low

tBVPH

BS1 Valid before PAGEL High

tPHPL

PAGEL Pulse Width High

150

tPLBX

BS1 Hold after PAGEL Low

tWLBX

BS2/1 Hold after WR Low

tPLWL

PAGEL Low to WR Low

tBVWL

BS1 Valid to WR Low

tWLWH

WR Pulse Width Low

150

tWLRL

WR Low to RDY/BSY Low

μs

tWLRH

WR Low to RDY/BSY High(1)

3.7

4.5

tWLRH_CE

WR Low to RDY/BSY High for Chip Erase(2)

7.5

tXLOL

XTAL1 Low to OE Low

ATtiny261A Datasheet(PDF) 191 Page - ATMEL Corporation

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