TAS5713PHPR datasheet(24/63 Pages) TI

24 / 63 page

TAS5713

SLOS637 – DECEMBER 2009

www.ti.com

The TAS5713 has robust clock error handling that uses the built-in trimmed oscillator clock to quickly detect

changes/errors. Once the system detects a clock change/error, it mutes the audio (through a single-step mute)

and then forces PLL to limp using the internal oscillator as a reference clock. Once the clocks are stable, the

system autodetects the new rate and revert to normal operation. During this process, the default volume is

restored in a single step (also called hard unmute). The ramp process can be programmed to ramp back slowly

(also called soft unmute) as defined in volume register (0x0E).

SERIAL DATA INTERFACE

Serial data is input on SDIN. The PWM outputs are derived from SDIN. The TAS5713 DAP accepts serial data in

16-, 20-, or 24-bit left-justified, right-justified, and I2S serial data formats.

PWM SECTION

The TAS5713 DAP device uses noise-shaping and customized nonlinear correction algorithms to achieve high

power efficiency and high-performance digital audio reproduction. The DAP uses a fourth-order noise shaper to

increase dynamic range and SNR in the audio band. The PWM section accepts 24-bit PCM data from the DAP

and outputs two BTL PWM audio output channels.

The PWM section has individual-channel dc-blocking filters that can be enabled and disabled. The filter cutoff

frequency is less than 1 Hz. Individual-channel de-emphasis filters for 44.1 kHz and 48 kHz are included and can

be enabled and disabled.

Finally, the PWM section has an adjustable maximum modulation limit of 93.8% to 99.2%.

For a detailed description of using audio processing features like DRC and EQ, see the User's Guide and

TAS570X GDE software development tool documentation.

SERIAL INTERFACE CONTROL AND TIMING

I2S Timing

I2S timing uses LRCLK to define when the data being transmitted is for the left channel and when it is for the

right channel. LRCLK is low for the left channel and high for the right channel. A bit clock running at 32, 48, or

64 × fS is used to clock in the data. There is a delay of one bit clock from the time the LRCLK signal changes

state to the first bit of data on the data lines. The data is written MSB-first and is valid on the rising edge of bit

clock. The DAP masks unused trailing data bit positions.

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TAS5713PHPR Datasheet(PDF) 24 Page - Texas Instruments