ADE7858 datasheet(45/76 Pages) AD

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Preliminary Technical Data

ADE7858

Rev. PrA | Page 45 of 76

powers, CF2 produces signals proportional to total reactive

powers and CF3 produces signals proportional to apparent

powers.

Table 18. CFxSEL, x=1,2,3 bits description

CFxSEL

Description

Registers latched when CFxLATCH=1

000

CFx signal proportional to the sum of total phase active powers

AWATTHR, BWATTHR, CWATTHR

001

CFx signal proportional to the sum of total phase reactive powers

AVARHR, BVARHR, CVARHR

010

CFx signal proportional to the sum of phase apparent powers

AVAHR, BVAHR, CVAHR

011 to 111

Reserved

Similar to the energy accumulation process, the energy to

frequency conversion is done in two stages. In the first stage,

the instantaneous phase powers obtained from the DSP at 8KHz

rate are shifted left 7 bits and then accumulated into an internal

generated and the threshold is subtracted from the internal

sign of the sum of phase powers (see Sign of sum of phase

powers in CFx data path section for details). The threshold is

the same threshold used in various active, reactive and

appearent energy accumulators in DSP, WTHR[47:0],

VARTHR[47:0] or VATHR[47:0], but this time it is shifted left 7

bits. The advantage of accumulating the instantaneous powers

at 1MHz rate is that the ripple at CFx pins is greatly diminished.

The second stage consists in a frequency divider by

CFxDEN[15:0], x=1, 2, 3, 16-bit unsigned registers. The values

of CFxDEN depend on the meter constant (MC), measured in

impulses/kwh and how much energy is assigned to 1LSB of

various energy registers: WATT-hr, VAR-hr, etc. Let’s suppose a

derivative of wh, [10n wh], n a positive or negative integer, is

desired as 1LSB of WATTHR. Then CFxDEN is:

]

kwh

imp

[

CFxDEN





(43)

The derivative of wh must be chosen in such a way to obtain a

CFxDEN greater than 1. If CFxDEN=1, then the CF stays active

low for only 1μsec, so this number should be avoided.

Fractional results cannot be accommodated by the frequency

converter, so the result of the division has to be rounded to the

nearest integer. If CFxDEN is set equal to 0, then the ADE7858

considers it as equal to 1.

The pulse output for all digital to frequency converters stays low

for 80ms if the pulse period is larger than 160ms (6.25Hz). If

the pulse period is smaller than 160ms and CFxDEN is an even

number, the duty cycle of the pulse output is exactly 50%. If the

pulse period is smaller than 160ms and CFxDEN is an odd

number, the duty cycle of the pulse output is

 %



 CFDEN

. The pulse output is active low and should

be preferably connected to an LED as shown in Figure 50.

Bits 11, 10, 9 (CF3DIS , CF2DIS and CF1DIS) of

CFMODE[15:0] register decide if the frequency converter

output is generated at CF3, CF2 or CF1 pins. When bit CFxDIS,

x=1, 2, 3 is set to 1, the default value, the CFx pin is disabled

and the pin stays high. When bit CFxDIS is cleared to 0, the

correspondent CFx pin output generates an active low signal.

Bits 16, 15, 14 (CF3, CF2, CF1) in interrupt mask register

MASK0[31:0] manage CF3, CF2 and CF1 related interrupts.

When CFx, x=1, 2, 3 bits are set, whenever a high to low

transition at corresponding frequency converter output occurs,

an interrupt

IRQ is triggered and a status bit in

STATUS0[31:0] register is set to 1. The interrupt is available

even if the CFx output is not enabled by CFxDIS bits in

CFMODE[15:0].

CFx pin

Figure 50. CF pin recommended connection

Synchronizing energy registers with CFx outputs

The ADE7858 contains a feature that allows synchronizing the

content of phase energy accumulation registers with the

generation of a CFx pulse. When a high to low transition at one

frequency converter output occurs, the content of all internal

phase energy registers that relate to the power being output at

CFx pin is latched into hr registers and then is reset to 0. See

Table 18 for the list of registers that are latched based on

CFxSEL[2:0] bits in CFMODE[15:0] register. All 3 phase

registers are latched independent of TERMSELx bits of

COMPMODE[15:0] register. The process is shown in Figure 51

for CF1SEL[2:0]=010 (apparent powers contribute at CF1 pin)

and CFCYC=2.

CFCYC[7:0] 8-bit unsigned register contains the number of

high to low transitions at frequency converter output between

two consecutive latches. Writing a new value into CFCYC[7:0]

avoided.

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