ADE7858 datasheet(28/76 Pages) AD

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ADE7858

Preliminary Technical Data

Rev. PrA| Page 28 of 76

bit 24 (IPPHASE[0]) of IPEAK[31:0] is cleared to 0 and bit 25

(IPPHASE[1]) of IPEAK[31:0] is set to 1. Figure 31 presents the

composition of IPEAK and VPEAK registers.

24 bit unsigned number

00000

peak detected on

phase A

peak detected on

phase B

peak detected on

phase C

IPPHASE/

VPPHASE bits

Figure 31.Composition of IPEAK[31:0] and VPEAK[31:0] registers

Peak value written into IPEAK at

the end of first PEAKCYC

period

End of first

PEAKCYC=16 period

End of second

PEAKCYC=16 period

Bit 24 of IPEAK

cleared to 0 at

the end of

second

PEAKCYC

period

Bit 25 of IPEAK

set to 1 at the

end of second

PEAKCYC

period

Peak value written into IPEAK at

the end of second PEAKCYC

period

Phase A

current

Phase B

current

Bit 24 of IPEAK

Figure 32. ADE7858 Peak Level Detection

Figure 32 shows how the ADE7858 records the peak value on

the current channel when measurements on phases A and B are

enabled (bits PEAKSEL[2:0] in MMODE[7:0] are 011).

PEAKCYC[7:0] is set to 16, meaning that the peak

measurement cycle is 4 line periods. The maximum absolute

value of phase A is the greatest during the first 4 line periods

(PEAKCYC=16), so the maximum absolute value is written into

the less significant 24 bits of IPEAK[31:0] register and bit 24

(IPPHASE[0]) of IPEAK[31:0] register is set to 1 at the end of

the period. This bit remains 1 for the duration of the second

PEAKCYC period of 4 line cycles. The maximum absolute value

of phase B is the greatest during the second PEAKCYC period,

so the maximum absolute value is written into the less

significant 24 bits of IPEAK register and bit 25 (IPPHASE[1]) in

IPEAK register is set to 1 at the end of the period.

At the end of the peak detection period in the current channel,

bit 23 (PKI) in STATUS1[31:0] register is set to 1. If bit 23 (PKI)

in MASK1[31:0] register is set, then

IRQ

interrupt pin is driven

low at the end of PEAKCYC period and the status bit 23 (PKI)

in STATUS1[31:0] is set to 1. In a similar way, at the end of the

peak detection period in the voltage channel, bit 24 (PKV) in

STATUS1[31:0] register is set to 1. If bit 24 (PKV) in

MASK1[31:0] register is set, then

IRQ interrupt pin is driven

low at the end of PEAKCYC period and the status bit 24 (PKV)

in STATUS1[31:0] is set to 1. To find the phase that triggered

the interrupt, one of IPEAK[31:0] or VPEAK[31:0] registers is

read immediately after reading STATUS1[31:0]. Then the status

bits are cleared and

IRQ pin is set back high by writing

STATUS1[31:0] register with the status bit set to 1.

Note that the internal zero-crossing counter is always active. By

setting bits 4, 3, 2 (PEAKSEL[2:0]) in MMODE[7:0] register, the

first peak detection result is, therefore, not done across a full

PEAKCYC period. Writing to the PEAKCYC[7:0] register when

the PEAKSEL[2:0] bits are set resets the zero-crossing counter,

thus ensuring that the first peak detection result is obtained

across a full PEAKCYC period.

Overvoltage and Overcurrent Detection

Phase A

Voltage Channel

OVLVL[23:0]

Bit 18 (OV) of

STATUS1

Overvoltage

detected

STATUS1[18] and

PHSTATUS[9]

cancelled by a write

of STATUS1 with

OV bit set

Bit 9 (OVPHASE)

of PHSTATUS

Figure 33. ADE7858 Overvoltage Detection

The ADE7858 detects when the instantaneous absolute value

measured on the voltage and current channels becomes greater

than thresholds set in OVLVL[23:0] and OILVL[23:0] 24-bit

unsigned registers. If bit 18 (OV) in MASK1[31:0] register is

set,

IRQ

interrupt pin is driven low in case of an overvoltage

event. There are two status flags set when

IRQ

interrupt pin is

driven low: bit 18 (OV) in STATUS1[31:0] register and one of

bits 11, 10, 9 (OVPHASE[2:0]) in PHSTATUS[15:0] register

identifying the phase that generated the overvoltage. The status

bit 18 (OV) in STATUS1[31:0] register and all bits 11, 10, 9

(OVPHASE[2:0]) in PHSTATUS[15:0] register are cleared and

IRQ

pin is set back high by writing STATUS1[31:0] register

with the status bit set to 1. Figure 33 presents overvoltage

detection in phase A voltage. Whenever the absolute

instantaneous value of the voltage goes above the threshold

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