34844 datasheet(15/37 Pages) FREESCALE

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Analog Integrated Circuit Device Data

Freescale Semiconductor

34844

FUNCTIONAL DESCRIPTION

FUNCTIONAL INTERNAL BLOCK DESCRIPTION

Also the device has a precharge voltage that add 0.5 Volts

to the Boost, cycle by cycle of the PWM. It helps the boost to

respond faster every time the load turns back on again.

CURRENT MIRROR

The programmable current mirror matches the current in

10 LED strings to within 2%. The maximum current is set

using a resistor to GND from the ISET pin. This can be scaled

down using the I2C interface to 255 levels.

Zero current is achieved by turning off the LED Driver by

I2C (registers CHENx = 0h) for a duty cycle from 0% to 99%

or by pulling PWM pin low regardless of the duty cycle.

I2C capability allows the channels to be controlled

individually or in parallel.

Current on LED Channel (PIN and NIN mode disabled)

Eqn. 1

In the off state, the LEDs current is set to 0 and the boost

converter stops switching.

This feature allows to drive more than 50 mA of current by

connecting the LED string to 2 or more LED channels in

parallel. For example; if the application requires to drive 5

channels at 100 mA, then the bottom of each LED string

should be connected to two channels in order to duplicate the

current capability (Example: CH0+CH1 = 100 mA).

PWM GENERATOR

The PWM generator can operate in either master or slave

modes, as set by the M/~S pin.

In master mode, the internal PWM generator frequency is

programmed through the I2C interface (registers FPWM).

The default programmed value set the number of 25 kHz

clocks (40

μs) in one PWM cycle. The 18-bit resolution allows

minimum PWM frequencies of 100 Hz to be programmed.

The resulting frequency is output on the CK pin.

PWM Frequency

Eqn. 2

In slave mode, the CK pin acts as an input. The internal

digital PLL uses this frequency as the PWM frequency. By

setting one device as master, and connecting the CK output

to the input on a number of slave configured devices, all

PWM frequencies are synchronized together.

The duty cycle of the PWM waveform in both master and

slave modes is set using a second register on the I2C

interface (register DPWM), and can be controlled from 100%

duty cycle to 1/256 Tpwm = 0.39%. Zero percent of duty cycle

is achieved by turning LED drivers off (register CHENx = 0h)

or pulling PWM pin low.

An external PWM can also be used. The PWM input is

'AND'ed with the internal signal. By setting the serial interface

to 100% duty cycle (default), the external pin has full control

of the PWM duty cycle. This pin can also be used to modulate

the LED at a lower frequency than the PWM dimming

frequency (Minimum pulse width = 150 ns).

A pulsed mode can also be programmed using the I2C

interface (STROBE bit = 1). In this mode, each rising edge of

the PWM signal turns on the next channel, while turning off

all other channels. The duration that the channel is

illuminated is set by the duty cycle of the PWM input pin. This

can be used to scan the output channels.

DISABLING LED CHANNELS

MC34844 allows the user to enable and disable each of

the 10 channels separately by writing the corresponding

CHENx bit on Registers 08 and 09 thru I2C.

When a channel is disabled thru I2C prior the device starts

to operate, the corresponding LED driver is disabled but the

feedback circuit is still connected. This may interfere with the

operation of the dynamic headroom control (DHC) which can

lead to erratic output voltage regulation. For this condition,

the output voltage may ramp up to the OVP level if the

voltage on the LED driver is not substantially above the DHC

regulation voltage (0.75 V typ). Because of this operation

under I2C/SMBUS Mode, we recommend to connect the

unused channels to VDC2 thru a100 kohm resistor and also

follow the below powering up sequence:

1. PWM pin = Low.

2. Power up the part.

3. Program the I2C commands and disable the unused

channels.

4. Enable the Boost and current drivers by taking PWM

pin to HIGH.

This previous device's operation does not happen when all

channels are being used because the voltage across the LED

drivers is always equal or higher than the DHC regulation

voltage (0.75 V typ). For this condition, the user can disable/

enable any of the channels thru I2C without causing any

erratic behavior but the FAIL pin cannot be cleared. If FAIL

pin is to be cleared thru I2C, it will be necessary to use the

suggested configuration shown at the FAIL PIN session.

FAIL PIN

If a LED fails open in any of the LED strings, the voltage in

that particular LED channel will be close to ground and the

LED open failure is detected. When this happens, a failure is

registered, the FAIL pin is set to its high-impedance stage,

and the channel is turned off.

The FAIL pin cannot be cleared for manual mode unless a

complete power on reset is applied. However for I2C/SMBUS

mode, the FAIL pin is cleared by disabling the malfunction

channels (CHENx = 0) and clearing the failure bit (CLRFAIL

bit = 1).

If the application only requires clearing the failure for the

floating or unused channels, then the unused channels must

be connected to VDC2 thru a 100 kohm resistor to avoid

Current A

[]

ICH RegisterValue

[]

RSET ohms

[]

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PWMFrequency Hz

[]

19.2Mhz

FPWM RegisterValue

[]

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34844 Datasheet(PDF) 15 Page - Freescale Semiconductor, Inc

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