33984B datasheet(27/38 Pages) FREESCALE

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Analog Integrated Circuit Device Data

Freescale Semiconductor

33984

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

SERIAL OUTPUT COMMUNICATION

(DEVICE STATUS RETURN DATA)

When the CS pin is pulled low, the output status register is

loaded. Meanwhile, the data is clocked out MSB- (OD7-) first

as the new message data is clocked into the SI pin. The first

eight bits of data clocking out of the SO, and following a CS

transition, are dependant upon the previously written SPI

word.

Any bits clocked out of the SO pin after the first eight will

be representative of the initial message bits clocked into the

SI pin since the CS pin first transitioned to a Logic [0]. This

feature is useful for daisy chaining devices as well as

message verification.

A valid message length is determined following a CS

transition of Logic [0] to Logic [1]. If there is a valid message

length, the data is latched into the appropriate registers. A

valid message length is a multiple of eight bits. At this time,

the SO pin is tri-stated and the fault status register is now

able to accept new fault status information.

The output status register correctly reflects the status of

the STATR-selected register data at the time that the CS is

pulled to a Logic [0] during SPI communication and/or for the

period of time since the last valid SPI communication, with

the following exceptions:

• The previous SPI communication was determined to be

invalid. In this case, the status will be reported as

though the invalid SPI communication never occurred.

• Battery transients below 6.0 V resulting in an under-

voltage shutdown of the outputs may result in incorrect

data loaded into the status register. The SO data

transmitted to the MCU during the first SPI

communication following an under-voltage VPWR

condition should be ignored.

•The RST pin transition from a Logic [0] to Logic [1] while

the WAKE pin is at Logic [0] may result in incorrect data

loaded into the status register. The SO data transmitted

to the MCU during the first SPI communication following

this condition should be ignored.

SERIAL OUTPUT BIT ASSIGNMENT

The 8 bits of serial output data depend on the previous

serial input message, as explained in the following

paragraphs. Table 16 summarizes the SO register content.

Bit OD7 reflects the state of the watchdog bit (D7)

addressed during the prior communication. The value of the

previous D7 will determine which output the status

information applies to for the Fault (FLTR), SOCHLR,

CDTOLR, and DICR registers. SO data will represent

information ranging from fault status to register contents,

user selected by writing to the STATR bits D2:D0. Note that

the SO data will continue to reflect the information for each

output (depending on the previous D7 state) that was

selected during the most recent STATR write until changed

with an updated STATR write.

Previous Address SOA[2:0]=000

If the previous three MSBs are 000, bits OD6:OD0 will

reflect the current state of the Fault register (FLTR)

corresponding to the output previously selected with the bit

OD7 (Table 17).

Previous Address SOA[2:0]=001

Data in bits OD1:OD0 contain CSNS0 EN and IN0_SPI

programmed bits, respectively. Data in bits OD3:OD2 contain

CSNS0 EN and IN0_SPI programmed bits, respectively.

Previous Address SOA[2:0]=010

The data in bit OD3 contain the programmed over-current

high detection level (refer to Table 12), and the data in bits

OD2:OD0 contain the programmed over-current low

detection levels (refer to Table 13).

Table 16. Serial Output Bit Map Description

Previous STATR

D7, D2, D1, D0

Serial Output Returned Data

SOA3 SOA2 SOA1 SOA0

OD7

OD6

OD5

OD4

OD3

OD2

OD1

OD0

OTFs

OCHFs

OCLFs

OLFs

UVF

OVF

FAULTs

CSNS1 EN

IN1_SPI

CSNS0 EN

IN0_SPI

SOCHs

SOCL2s

SOCL1s

SOCL0s

OL_DIS s

CD_DIS s

OCLT1s

OCLT0s

FAST SR s CSNS high s

IN DIS s

A/Os

FSM_HS0

OSD2

OSD1

OSD0

FSM_HS1

WDTO

WD1

WD0

IN1 Pin

IN0 Pin

FSI Pin

WAKE Pin

–

UV_dis

OV_dis

–

See Table 1

–

s = Selection of output: Logic [0] = HS0, Logic [1] = HS1.

x = Don’t care.

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