33984B datasheet(20/38 Pages) FREESCALE

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Analog Integrated Circuit Device Data

Freescale Semiconductor

33984

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

The 33984 has four operating modes: Sleep, Normal,

Fault, and Fail-safe. Table 6 summarizes details contained in

succeeding paragraphs.

SLEEP MODE

The default mode of the 33984 is the Sleep mode. This is

the state of the device after first applying battery voltage

(VPWR), prior to any I/O transitions. This is also the state of

the device when the WAKE and RST are both Logic [0]. In the

Sleep mode, the output and all unused internal circuitry, such

as the internal 5.0 V regulator, are off to minimize current

draw. In addition, all SPI-configurable features of the device

are as if set to Logic [0]. The device will transition to the

Normal or Fail-safe operating modes based on the WAKE

and RST inputs as defined in Table 6.

NORMAL MODE

The 33984 is in Normal mode when:

•VPWR is within the normal voltage range.

• RST pin is Logic [1].

• No fault has occurred.

FAIL-SAFE AND WATCHDOG

If the FSI input is not grounded, the watchdog timeout

detection is active when either the WAKE or RST input pin

transitions from Logic [0] to Logic [1]. The WAKE input is

capable of being pulled up to VPWR with a series of limiting

resistance that limits the internal clamp current according to

the specification.

The watchdog timeout is a multiple of an internal oscillator

and is specified in Table 15. As long as the WD bit (D7) of an

incoming SPI message is toggled within the minimum

watchdog timeout period (WDTO), based on the

programmed value of the WDR the device will operate

normally. If an internal watchdog timeout occurs before the

WD bit, the device will revert to a Fail-safe mode until the

device is reinitialized.

During the Fail-safe mode, the outputs will be ON or OFF

depending upon the resistor RFS connected to the FSI pin,

regardless of the state of the various direct inputs and modes

(Table 7). In this mode, the SPI register content is retained

except for over-current high and low detection levels and

timing, which are reset to their default value (SOCL, SOCH,

and OCLT). Then the watchdog, over-voltage, over-

temperature, and over-current circuitry (with default value)

are fully operational.

The Fail-safe mode can be detected by monitoring the

WDTO bit D2 of the WD register. This bit is Logic [1] when the

device is in Fail-safe mode. The device can be brought out of

the Fail-safe mode by transitioning the WAKE and RST pins

from Logic [1] to Logic [0] or forcing the FSI pin to Logic [0].

Table 6 summarizes the various methods for resetting the

device from the latched Fail-safe mode.

If the FSI pin is tied to GND, the watchdog Fail-safe

operation is disabled.

LOSS OF VDD

If the external 5.0 V supply is not within specification, or

even disconnected, all register content is reset. The two

outputs can still be driven by the direct inputs IN1:IN0. The

33984 uses the battery input to power the output MOSFET

related current sense circuitry and any other internal logic

providing fail-safe device operation with no VDD supplied. In

this state, the watchdog, over-voltage, over-temperature, and

over-current circuitry are fully operational with default values.

Table 6. Fail-safe Operation and Transitions to Other

33984 Modes

Mode

WAKE RST WDTO

Comments

Sleep

Device is in Sleep mode.

All outputs are OFF.

Normal

Normal mode. Watchdog

is active if enabled.

Fault

The device is currently in

Fault mode. The faulted

output(s) is (are) OFF.

Fail-

safe

Yes

Watchdog has timed out

and the device is in Fail-

safe mode. The outputs

are as configured with

the RFS resistor

connected to FSI. RST

and WAKE must be

transitioned to Logic [0]

simultaneously to bring

the device out of the Fail-

safe mode or

momentarily tied the FSI

pin to ground.

x = Don’t care.

Table 7. Output State During Fail-safe Mode

RFS (k

Ω)

High Side State

Fail-safe mode Disabled

6.0

Both HS0 and HS1 OFF

HS0 ON, HS1 OFF

Both HS0 and HS1 ON

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