MPC5123 datasheet(56/86 Pages) FREESCALE

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MPC5121E/MPC5123 Data Sheet, Rev. 4

Electrical and Thermal Characteristics

Freescale Semiconductor

3.3.10

SATA PHY

1.5 Gbps SATA PHY Layer

See “Serial ATA: High Speed Serialized AT Attachment” Revision 1.0a, 7-January-2003.

3.3.11

FEC

AC Test Timing Conditions:

•

Output Loading

All Outputs: 25 pF

—

tdzfs

tdzfs = time_dzfs × T – (tskew1)

calculate and

programming

time_dzfs. 1

A9.70

tss

tss = time_ss × T – (tskew1 +tskew2)

calculate and

programming time_ss. 1

A9.71

tmli

tdzfs_mli

tdzfs_mli = max(time_dzfs, time_mli) × T –

(tskew1 +tskew2)

—

A9.72

tli

tli1

tli1 > 0

—

A9.73

tli

tli2

tli2 > 0

—

A9.74

tli

tli3

tli3 > 0

—

A9.75

tcvh

tcvh = (time_cvh × T) – (tskew1 +tskew2)

calculate and

programming

time_cvh. 1

A9.76

—

ton

toff

ton = time_on × T – tskew1

toff = time_off × T – tskew1

—

A9.77

1 See the MPC5121e Microcontroller Reference Manual.

Table 31. MII Rx Signal Timing

Sym

Description

Min

Max

Unit

SpecID

RXD[3:0], RX_DV, RX_ER to RX_CLK setup

—

A11.1

RX_CLK to RXD[3:0], RX_DV, RX_ER hold

—

A11.2

RX_CLK pulse width high

35%

65%

RX_CLK Period1

1 RX_CLK shall have a frequency of 25% of data rate of the received signal. See the IEEE 802.3 Specification.

A11.3

RX_CLK pulse width low

35%

65%

RX_CLK Period1

A11.4

Table 30. Timing Parameters UDMA Out Burst (continued)

ATA

Parameter

UDMA Out

Timing

Parameter

Value

How to meet

SpecID

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