LPC1766 datasheet(21/66 Pages) NXP

21 / 66 page

LPC1769_68_67_66_65_64_4

Product data sheet

Rev. 04 — 1 February 2010

21 of 66

NXP Semiconductors

LPC1769/68/67/66/65/64

32-bit ARM Cortex-M3 microcontroller

– Memory traffic optimized by buffering and pre-fetching.

• Enhanced Ethernet features:

– Receive filtering.

– Multicast and broadcast frame support for both transmit and receive.

– Optional automatic Frame Check Sequence (FCS) insertion with Cyclic

Redundancy Check (CRC) for transmit.

– Selectable automatic transmit frame padding.

– Over-length frame support for both transmit and receive allows any length frames.

– Promiscuous receive mode.

– Automatic collision back-off and frame retransmission.

– Includes power management by clock switching.

– Wake-on-LAN power management support allows system wake-up: using the

receive filters or a magic frame detection filter.

• Physical interface:

– Attachment of external PHY chip through standard RMII interface.

– PHY register access is available via the MIIM interface.

7.12 USB interface (LPC1769/68/66/65/64 only)

The Universal Serial Bus (USB) is a 4-wire bus that supports communication between a

host and one or more (up to 127) peripherals. The host controller allocates the USB

bandwidth to attached devices through a token-based protocol. The bus supports hot

plugging and dynamic configuration of the devices. All transactions are initiated by the

host controller.

The USB interface includes a device, Host, and OTG controller with on-chip PHY for

device and Host functions. The OTG switching protocol is supported through the use of an

external controller. Details on typical USB interfacing solutions can be found in

Section 14.1.

Remark: The LPC1764 includes a device controller only.

7.12.1 USB device controller

The device controller enables 12 Mbit/s data exchange with a USB Host controller. It

consists of a register interface, serial interface engine, endpoint buffer memory, and a

DMA controller. The serial interface engine decodes the USB data stream and writes data

to the appropriate endpoint buffer. The status of a completed USB transfer or error

condition is indicated via status registers. An interrupt is also generated if enabled. When

enabled, the DMA controller transfers data between the endpoint buffer and the on-chip

SRAM.

7.12.1.1

Features

• Fully compliant with USB 2.0 specification (full speed).

• Supports 32 physical (16 logical) endpoints with a 4 kB endpoint buffer RAM.

• Supports Control, Bulk, Interrupt and Isochronous endpoints.

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