AS3525 datasheet(128/194 Pages) AMSCO

128 / 194 page

AS3525-A/-B C22O22

Data Sheet, Confidential

www.austriamicrosystems.com

Revision 1.13

128

- 194

7.4.4.4

Table 106 CVDD / DCDC3 Register

Name

Base

Default

CVDD / DCDC 3

I2C audio master

0x00

Charge Pump and 3V DCDC Register

Offset: 0x21

This register is reset at a DVDD-POR.

Bit

Bit Name

Default

Access

Bit Description

CP_SW

R/W

charge pump / length regulator switch margin reduction

0: margin set to 200/300 mV

1: margin reduced to 150/225 mV (automatic switching to

length regulator is done “later”, at a lower input voltage)

CP_on

R/W

0: normal operation

1: keeps Mode 3 charge pump always on

Please note that bit 2 = “0”, overrides bit 6.

Core voltage generation mode

0: CP is working

1: LREG is working

LREG_CPnot

For production testing purpose only, in normal application

mode this bit must always be written with “0”.

4:3

DCDC3p

R/W

DCDC3 Vout programming (BVDD)

00: 3.6V

01: 3.2V

10: 3.1V

11: 3.0V

LREG_off

R/W

0: keeps Mode2 (length regulator always on)

1: normal operation

1:0

CVDDp

R/W

CVDD trimming:

00: 1.2V

01: 1.15V

10: 1.10V

11: 1.05V

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