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AS3525 Datasheet(PDF) 157 Page - ams AG |
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AS3525 Datasheet(HTML) 157 Page - ams AG |
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157 / 194 page ![]() AS3525-A/-B C22O22 Data Sheet, Confidential © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 157 - 194 7.4.18 Interrupt Generation 7.4.18.1 General All interrupt sources can get enabled or disabled by corresponding bits in the 3 IRQ-bytes. By default no IRQ source is enabled. The IRQ output can get configured to be PUSH/PULL or OPEN_DRAIN and ACTIVE_HIGH or ACTIVE LOW with 2 bits in IRQ_ENRD_2 register (0x27). Default state is open drain and active_low. 7.4.18.2 IRQ Source Interpretation There are 3 different modules to process interrupt sources: 7.4.18.3 LEVEL The IRQ output is kept active as long as the interrupt source is present and this IRQ-Bit is enabled 7.4.18.4 EDGE The IRQ gets active with a high going edge of this source. The IRQ stays active until the corresponding IRQ-Register gets read. 7.4.18.5 STATUS CHANGE The IRQ gets active when the source-state changes. The change bit and the status can be read to notice which interrupt was the source. The IRQ stays active until the corresponding interrupt register gets read. 7.4.18.6 De-bouncer There is a de-bounc function implemented for USB and CHARGER. Since these 2 signals can be unstable for the phase of plug-in or unplug, a de- bounce time of 512ms/256ms/128ms can be selected by 2 bits in the IRQ_ENRD2 register (0x27h). Table 145 First Interrupt Register Name Base Default IRQ_ENRD_0 I2C audio master 0x00 First Interrupt Register Offset: 0x25 Please be aware that writing to this register will enable/disable the corresponding interrupts, while with reading you get the actual interrupt status and will clear the register at the same time. It is not possible to read back the interrupt enable/disable settings. This register is reset at a DVDD-POR. Bit Bit Name Default Access Bit Description 0 W battery over-temperature interrupt setting 0: disable 1: enable The interrupt must not be enabled if the charger block and battery temperature supervision is disabled 7 CHG_tmphigh (level) x R Battery over-temperature interrupt reading 0: battery temperature below 55°C 1: battery temperature was too high and the charger was turned off. The charger will be turned on again, when the temperature gets below 50°C 0 W Battery end of charge interrupt setting 0: disable 1: enable The interrupt must not be enabled if the charger block is disabled 6 CHG_endofch (edge) x R Battery end of charge interrupt reading 0: battery charging in progress 1: charging is complete, turn charger off To check end of charge again the charger has to be turned on. 5 CHG_status x R 0: no charger input source connected 1: charger input source connected, also valid if charger is connected during wakeup |
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