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AS3525 Datasheet(PDF) 158 Page - ams AG

Part # AS3525
Description  Advanced Audio Processor System
PDF  194 Pages
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Manufacturer  AMSCO [ams AG]
Direct Link  http://www.ams.com
Logo AMSCO - ams AG

AS3525 Datasheet(HTML) 158 Page - ams AG

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AS3525-A/-B C22O22
Data Sheet, Confidential
© 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.
www.austriamicrosystems.com
Revision 1.13
158
- 194
Name
Base
Default
IRQ_ENRD_0
I2C audio master
0x00
First Interrupt Register
Offset: 0x25
Please be aware that writing to this register will enable/disable the corresponding
interrupts, while with reading you get the actual interrupt status and will clear the
register at the same time. It is not possible to read back the interrupt enable/disable
settings. This register is reset at a DVDD-POR.
Bit
Bit Name
Default
Access
Bit Description
0
W
Charger input status change interrupt setting
0: disable
1: enable enables an interrupt on a low to high or high to low
change of CHG_IN pin. The thresholds are set in
4
CHG_changed
(status change)
x
R
Charger input status change interrupt reading
0: charger input status not changed
1: charger input status changed, check CHG_status
3
USB_status
x
R
0: no USB input connected
1: USB input connected, also valid if USB is connected during
wakeup
0
W
USB input status change interrupt setting
0: disable
1: enables an interrupt on a low to high or high to low change
of VBUS pin. The threshold can be set in the USB_UTIL
register (0x17)
2
USB_changed
(status change)
x
R
USB input status change interrupt reading
0: USB input status not changed
1: USB input status changed, check USB_status
0
W
Real time clock supply interrupt setting
0: disable
1: enable
1
RVDD_waslow
(level)
x
R
Real time clock supply interrupt reading
0: RTC supply o.k.
1: RTC supply was low, RTC not longer valid
The interrupt gets set during power-up even if the interrupt is
not enabled. For a valid reading, the interrupt has to be
enabled first.
0
W
Supervisor BVDD interrupt setting
0: disable
1: enable
0
BVDD_islow
x
R
Supervisor BVDD interrupt setting
0: BVDD is above brown out level
1:BVDD has reached brown out level
The threshold can be set in the SUPERVISOR register (0x24)



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