AS3525 datasheet(183/194 Pages) AMSCO

183 / 194 page

AS3525-A/-B C22O22

Data Sheet, Confidential

www.austriamicrosystems.com

Revision 1.13

183

- 194

8.3.2 CTBGA144 Ball List

Table 162 CTBGA144 Ball List

Ball Nr.

BGA144

Ball Name

PAD Type

I/O

Ball Description

XRES

resetext_n

D IN ST

XRES is generated by the PMU subsystem and connected to

reset input (active low) on the BGA

clk_ext

D IN ST PD

external clock input (10-26MHz)

clk_sel

D IN ST PD

clock select

0 (low): clock from internal oscillator is used

1 (high): clock from pad clk_ext is used

tmsel

D IN ST PD

test mode select

For testing purpose only, has to be set to “0”.

id_dig

D IN ST (PU)

USB mini receptacle identifier

Has to be connected to USB jack ID pin.

Port A

xpa[0]

D IO ST PD LSR IO

GPIO IO, Port A

xpa[1]

D IO ST PD LSR IO

GPIO IO, Port A

xpa[2]

D IO ST PD LSR IO

GPIO IO, Port A

xpa[3]

D IO ST PD LSR IO

GPIO IO, Port A

xpa[4]

D IO ST PD LSR IO

GPIO IO, Port A

xpa[5]

D IO ST PD LSR IO

GPIO IO, Port A

xpa[6]

D IO ST PD LSR IO

GPIO IO, Port A

xpa[7]

D IO ST PD LSR IO

GPIO IO, Port A

Port B / DISPLAY / UART

xpb[0]

GPIO IO, Port B

mpmc_stcs1mw[0

static memory chip memory width setting for boot loader

0: 8 bit data bus

1: 16 bit data bus

The value is latched at reset.

dbop_c0

D IO ST PD LSR

DISPLAY control output

xpb[1]

GPIO IO, Port B

mpmc_stcs1pol*

static memory chip select polarity setting for boot loader

0: active LOW chip select

1: active high chip select

The value is latched at reset.

dbop_c1

D IO ST PD LSR

DISPLAY control output

xpb[2]

GPIO IO, Port B

mpmc_stcs1pb*

static memory byte lane polarity setting for boot loader

0: HIGH for reads, LOW for writes, used for we_n access

1: LOW for reads, LOW for writes, used for upper and lower byte

access

The value is latched at reset.

dbop_c2

D IO ST PD LSR

DISPLAY control output

xpb[3]

GPIO IO, Port B

mpmc_rel1config*

test mode configuration (for testing purpose only !!!)

The value is latched at reset.

dbop_c3

D IO ST PD LSR

DISPLAY control output

xpb[4]

GPIO IO, Port B

dbop_d[8]

D IO ST PD LSR

DISPLAY data input/output (high byte)

xpb[5]

GPIO IO, Port B

dbop_d[9]

D IO ST PD LSR

DISPLAY data input/output (high byte)

xpb[6]

D IO ST PU LSR IO

GPIO IO, Port B

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