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AS3525 Datasheet(PDF) 186 Page - ams AG |
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AS3525 Datasheet(HTML) 186 Page - ams AG |
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186 / 194 page  AS3525-A/-B C22O22 Data Sheet, Confidential © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 186 - 194 Ball Nr. BGA144 Ball Name PAD Type I/O Ball Description naf_d[14] IO NAND FLASH data line (high byte) D11 D IO ST PD LSR naf_d[15] IO NAND FLASH data line (high byte) D10 D IO ST PD LSR naf_cle O NAND FLASH command latch enable E10 D IO ST LSR naf_ale O NAND FLASH address latch enable E9 D IO ST LSR naf_wp_n O NAND FLASH write protect not E8 D IO ST PD LSR naf_ce0_n O NAND FLASH chip enable E7 D IO ST LSR E6 naf_ce1_n D IO ST LSR O NAND FLASH chip enable naf_ce2_n O NAND FLASH chip enable J7 D IO ST LSR naf_ce3_n O NAND FLASH chip enable J8 D IO ST LSR naf_we_n O NAND FLASH write enable not E5 D IO ST LSR naf_re_n O NAND FLASH read enable not E11 D IO ST LSR naf_bsy_n I NAND FLASH ready / busy not F9 D IO ST LSR I2S Input i2si_sdata_in I I2S data input data input from external audio ADC A3 spdif_data_in D IN ST PD I SPDIF data input data input for SPDIF to I2S conversion Audio Subsystem IRQ J5 INTRQ intrq DO D IN ST O I used by the audio/PMU subsystem to interrupt the digital core, INTRQ and intrq are connected on the BGA JTAG Debugging IF C1 jtag_trst_n D IN ST PD I JTAG reset not C3 jtag_tms D IN ST PU I JTAG mode select B2 jtag_tck D IN ST PU I JTAG clock B1 jtag_tdi D IN ST PU I JTAG data input B3 jtag_tdo D IO ST PU LSR O JTAG data output DBOP A1 dbop_d[12] D IO ST PD LSR IO DISPLAY data input/output (high byte) A2 dbop_d[13] D IO ST PD LSR IO DISPLAY data input/output (high byte) A9 dbop_d[14] D IO ST PD LSR IO DISPLAY data input/output (high byte) B9 dbop_d[15] D IO ST PD LSR IO DISPLAY data input/output (high byte) USB 2.0 OTG F2 vdda33 PWP_VD_ ANA_3V P USB 3.3V analog power supply for common block F1 vssa33 PWP_VS_ ANA_3V P USB 3.3V analog ground supply for common block |
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