PCF2127ATSLASH1 datasheet(26/80 Pages) NXP

26 / 80 page

PCF2127A_2

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Product data sheet

Rev. 02 — 7 May 2010

26 of 80

NXP Semiconductors

PCF2127A

Integrated RTC, TCXO and quartz crystal

8.8 Reset function

The PCF2127A has an active LOW open-drain output reset pin (RST). The reset output is

activated at Power-On Reset (POR) and whenever the oscillator is stopped (see

Section 8.7).

8.8.1 Power-On Reset (POR)

The POR is active whenever the oscillator is stopped. The oscillator is also considered to

be stopped during the time between power-on and stable crystal resonance (see

Figure 14). This time may be in the range of 200 ms to 2 s depending on temperature and

supply voltage. Whenever an internal reset occurs, the oscillator stop flag is set (OSF set

logic 1).

After POR, the following mode is entered:

• 32.768 kHz CLKOUT active

• Power-On Reset Override (PORO) available to be set

• 24 hour mode is selected

• Battery switch-over is enabled

• Battery low detection is enabled

• Extra power fail detection is enabled

The register values after power-on are shown in Table 4.

8.8.2 Power-On Reset Override (PORO)

The POR duration is directly related to the crystal oscillator start-up time. Due to the long

start-up times experienced by these types of circuits, a mechanism has been built in to

disable the POR and therefore speed up on-board test of the device.

Fig 14. Dependency between POR and oscillator

013aaa243

chip in reset

chip not in reset

VDD

oscillation

RST

PCF2127AT/1 Datasheet(PDF) 26 Page - NXP Semiconductors