PCF2127ATSLASH1 datasheet(50/80 Pages) NXP

50 / 80 page

PCF2127A_2

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Product data sheet

Rev. 02 — 7 May 2010

50 of 80

NXP Semiconductors

PCF2127A

Integrated RTC, TCXO and quartz crystal

8.13.6 Timestamp interrupts

Interrupt generation from the timestamp function is controlled using the TSIE bit (register

Control_2). If TSIE is enabled the INT pin follows the status of the flags TSFx. Clearing

the flags TSFx immediately clears INT. No pulse generation is possible for timestamp

interrupts.

8.13.7 Battery switch-over interrupts

Generation of interrupts from the battery switch-over is controlled via the BIE bit (register

Control_3). If BIE is enabled, the INT pin follows the status of bit BF in register Control_3

(see Table 52). Clearing BF immediately clears INT. No pulse generation is possible for

battery switch-over interrupts.

8.13.8 Battery low detection interrupts

Generation of interrupts from the battery low detection is controlled via the BLIE bit

(register Control_3). If BLIE is enabled the INT pin will follow the status of bit BLF (register

Control_3). The interrupt is cleared when the battery is replaced (BLF is logic 0) or when

bit BLIE is disabled (BLIE is logic 0). BLF is read only and therefore cannot be cleared via

the interface.

PCF2127AT/1 Datasheet(PDF) 50 Page - NXP Semiconductors