P89LPC9321 datasheet(48/70 Pages) NXP

48 / 70 page

P89LPC9321_1

Product data sheet

Rev. 01 — 9 December 2008

48 of 70

NXP Semiconductors

P89LPC9321

8-bit microcontroller with accelerated two-clock 80C51 core

7.30.8 ISP

ISP is performed without removing the microcontroller from the system. The ISP facility

consists of a series of internal hardware resources coupled with internal ﬁrmware to

facilitate remote programming of the P89LPC9321 through the serial port. This ﬁrmware is

provided by NXP and embedded within each P89LPC9321 device. The NXP ISP facility

has made in-system programming in an embedded application possible with a minimum

of additional expense in components and circuit board area. The ISP function uses ﬁve

pins (VDD, VSS, TXD, RXD, and RST). Only a small connector needs to be available to

interface your application to an external circuit in order to use this feature.

7.30.9 Power-on reset code execution

The P89LPC9321 contains two special ﬂash elements: the Boot Vector and the Boot

Status bit. Following reset, the P89LPC9321 examines the contents of the Boot Status bit.

If the Boot Status bit is set to zero, power-up execution starts at location 0000H, which is

the normal start address of the user’s application code. When the Boot Status bit is set to

a value other than zero, the contents of the Boot Vector are used as the high byte of the

execution address and the low byte is set to 00H.

Table 8 shows the factory default Boot Vector setting for these devices. A factory-provided

boot loader is pre-programmed into the address space indicated and uses the indicated

boot loader entry point to perform ISP functions. This code can be erased by the user.

Remark: Users who wish to use this loader should take precautions to avoid erasing the

1 kB sector that contains this boot loader. Instead, the page erase function can be used to

erase the ﬁrst eight 64-byte pages located in this sector.

A custom boot loader can be written with the Boot Vector set to the custom boot loader, if

desired.

7.30.10 Hardware activation of the boot loader

The boot loader can also be executed by forcing the device into ISP mode during a

power-on sequence (see the P89LPC9321

User manual for speciﬁc information). This has

the same effect as having a non-zero status byte. This allows an application to be built that

will normally execute user code but can be manually forced into ISP operation. If the

factory default setting for the boot vector (1FH) is changed, it will no longer point to the

factory pre-programmed ISP boot loader code. After programming the ﬂash, the status

byte should be programmed to zero in order to allow execution of the user’s application

code beginning at address 0000H.

7.31 User conﬁguration bytes

Some user-conﬁgurable features of the P89LPC9321 must be deﬁned at power-up and

therefore cannot be set by the program after start of execution. These features are

conﬁgured through the use of the ﬂash byte UCFG1 and UCFG2. Please see the

P89LPC9321

User’s Manual for additional details.

Table 8.

Default boot vector values and ISP entry points

Device

Default

boot vector

Default

boot loader

entry point

Default boot loader

code range

1 kB sector

range

P89LPC9321

1FH

1F00H

1E00H to 1FFFH

1C00H to 1FFFH

P89LPC9321 Datasheet(PDF) 48 Page - NXP Semiconductors

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