| Electronic Components Datasheet Search |
|
P89LPC985FDH Datasheet(PDF) 35 Page - NXP Semiconductors |
|
|
|||||||||||||||||||||||||||||
P89LPC985FDH Datasheet(HTML) 35 Page - NXP Semiconductors |
|
35 / 85 page ![]() P89LPC980_982_983_985_2 © NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 02 — 8 February 2010 35 of 85 NXP Semiconductors P89LPC980/982/983/985 8-bit microcontroller with accelerated two-clock 80C51 core 7.10 CCLK wake-up delay The P89LPC980/982/983/985 has an internal wake-up timer that delays the clock until it stabilizes depending on the clock source used. If the clock source is any of the three crystal selections (low, medium and high frequencies) the delay is 1024 OSCCLK cycles plus 60 μsto100 μs. If the clock source is the internal RC oscillator, the delay is 200 μs to 300 μs. If the clock source is watchdog oscillator or external clock, the delay is 32 OSCCLK cycles. 7.11 CCLK modification: DIVM register The OSCCLK frequency can be divided down up to 510 times by configuring a dividing register, DIVM, to generate CCLK. This feature makes it possible to temporarily run the CPU at a lower rate, reducing power consumption. By dividing the clock, the CPU can retain the ability to respond to events that would not exit Idle mode by executing its normal program at a lower rate. This can also allow bypassing the oscillator start-up time in cases where Power-down mode would otherwise be used. The value of DIVM may be changed by the program at any time without interrupting code execution. 7.12 Low power select The P89LPC980/982/983/985 is designed to run at 18 MHz (CCLK) maximum. However, if CCLK is 8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to logic 1 to lower the power consumption further. On any reset, CLKLP is logic 0 allowing highest performance access. This bit can then be set in software if CCLK is running at 8 MHz or slower. (1) ±10 % at 400 kHz. Fig 9. Block diagram of oscillator control ÷2 002aae540 RTC ADC (P89LPC983/985) CPU WDT DIVM CCLK UART OSCCLK TIMER 2/ TIMER 3/ TIMER 4 PCLK TIMER 0 AND TIMER 1 HIGH FREQUENCY MEDIUM FREQUENCY LOW FREQUENCY XTAL1 XTAL2 RC OSCILLATOR WITH CLOCK DOUBLER WATCHDOG OSCILLATOR (7.3728 MHz/14.7456 MHz ± 1 %) PCLK RCCLK SPI I2C-BUS (400 kHz/25 kHz)(1) |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |