P89LPC985FDH datasheet(57/85 Pages) NXP

57 / 85 page

P89LPC980_982_983_985_2

Preliminary data sheet

Rev. 02 — 8 February 2010

57 of 85

NXP Semiconductors

P89LPC980/982/983/985

8-bit microcontroller with accelerated two-clock 80C51 core

7.29.6 ICP

ICP is performed without removing the microcontroller from the system. The ICP facility

consists of internal hardware resources to facilitate remote programming of the

P89LPC980/982/983/985 through a two-wire serial interface. The NXP ICP facility has

made in-circuit programming in an embedded application - using commercially available

programmers - possible with a minimum of additional expense in components and circuit

board area. The ICP function uses five pins. Only a small connector needs to be available

to interface your application to a commercial programmer in order to use this feature.

Additional details may be found in the P89LPC980/982/983/985 User manual.

7.29.7 IAP

IAP is performed in the application under the control of the microcontroller’s firmware. The

IAP facility consists of internal hardware resources to facilitate programming and erasing.

The NXP IAP has made in-application programming in an embedded application possible

without additional components. Two methods are available to accomplish IAP. A set of

predefined IAP functions are provided in a Boot ROM and can be called through a

common interface, PGM_MTP. Several IAP calls are available for use by an application

program to permit selective erasing and programming of flash sectors, pages, security

bits, configuration bytes, and device ID. These functions are selected by setting up the

microcontroller’s registers before making a call to PGM_MTP at FF03H. The Boot ROM

occupies the program memory space at the top of the address space from FF00H to

FEFFH, thereby not conflicting with the user program memory space.

In addition, IAP operations can be accomplished through the use of four SFRs consisting

of a control/status register, a data register, and two address registers. Additional details

may be found in the P89LPC980/982/983/985 User manual.

7.29.8 ISP

ISP is performed without removing the microcontroller from the system. The ISP facility

consists of a series of internal hardware resources coupled with internal firmware to

facilitate remote programming of the P89LPC980/982/983/985 through the serial port.

This firmware is provided by NXP and embedded within each P89LPC980/982/983/985

device. The NXP ISP facility has made in-system programming in an embedded

application possible with a minimum of additional expense in components and circuit

board area. The ISP function uses five pins (VDD, VSS, TXD, RXD, and RST). Only a small

connector needs to be available to interface your application to an external circuit in order

to use this feature.

7.29.9 Power-on reset code execution

The P89LPC980/982/983/985 contains two special flash elements: the Boot Vector and

the Boot Status bit. Following reset, the P89LPC980/982/983/985 examines the contents

of the Boot Status bit. If the Boot Status bit is set to zero, power-up execution starts at

location 0000H, which is the normal start address of the user’s application code. When

the Boot Status bit is set to a value other than zero, the contents of the Boot Vector are

used as the high byte of the execution address and the low byte is set to 00H.

Table 11 shows the factory default Boot Vector setting for these devices. A

factory-provided bootloader is pre-programmed into the address space indicated and

uses the indicated bootloader entry point to perform ISP functions. This code can be

erased by the user.

P89LPC985FDH Datasheet(PDF) 57 Page - NXP Semiconductors

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