PCF8566P datasheet(19/48 Pages) NXP

19 / 48 page

PCF8566_7

Product data sheet

Rev. 07 — 25 February 2009

19 of 48

NXP Semiconductors

PCF8566

Universal LCD driver for low multiplex rates

7.13 Sub-address counter

The storage of display data is conditioned by the contents of the subaddress counter.

Storage is allowed to take place only when the contents of the subaddress counter match

with the hardware subaddress applied to A0, A1 and A2. The subaddress counter value is

deﬁned by the device select command (see Table 14 and Table 21). If the contents of the

subaddress counter and the hardware subaddress do not match then data storage is

blocked but the data pointer will be incremented as if data storage had taken place. The

subaddress counter is also incremented when the data pointer overﬂows.

The storage arrangements described lead to extremely efﬁcient data loading in cascaded

applications. When a series of display bytes are sent to the display RAM, automatic

wrap-over to the next PCF8566 occurs when the last RAM address is exceeded.

Subaddressing across device boundaries is successful even if the change to the next

device in the cascade occurs within a transmitted character (such as during the 14th

display data byte transmitted in 1:3 multiplex mode).

7.14 Output bank selector

The output bank selector (see Table 15), selects one of the four bits per display RAM

address for transfer to the display register. The actual bit selected depends on the LCD

drive mode in operation and on the instant in the multiplex sequence.

• In 1:4 multiplex mode: all RAM addresses of bit 0 are selected, followed sequentially

by the contents of bit 1, bit 2 and then bit 3.

• In 1:3 multiplex mode: bits 0, 1 and 2 are selected sequentially.

• In 1:2 multiplex mode: bits 0 and 1 are selected.

• In the static mode: bit 0 is selected.

The PCF8566 includes a RAM bank switching feature in the static and 1:2 multiplex drive

modes. In the static drive mode, the bank select command may request the contents of

bit 2 to be selected for display instead of the contents of bit 0. In 1:2 multiplex drive mode,

the contents of bits 2 and 3 may be selected instead of bits 0 and 1. This enables

preparation of display information in an alternative bank and the ability to switch to it once

it has been assembled.

7.15 Input bank selector

The input bank selector loads display data into the display RAM based on the selected

LCD drive conﬁguration. Using the bank select command, display data can be loaded in

bit 2 into static drive mode or in bits 2 and 3 into 1:2 multiplex drive mode. The input bank

selector functions independently of the output bank selector.

7.16 Blinker

The display blinking capabilities of the PCF8566 are very versatile. The whole display can

be blinked at frequencies selected by the blink command. The blinking frequencies are

integer fractions of the clock frequency; the ratios between the clock and blinking

frequencies depend on the mode in which the device is operating (see Table 7).

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