PCF8566P datasheet(31/48 Pages) NXP

31 / 48 page

PCF8566_7

Product data sheet

Rev. 07 — 25 February 2009

31 of 48

NXP Semiconductors

PCF8566

Universal LCD driver for low multiplex rates

12. Dynamic characteristics

[1]

All timing values referred to VIH and VIL levels with an input voltage swing of VSS to VDD.

[2]

At fclk < 125 kHz, I2C-bus maximum transmission speed is derated.

Table 20.

Dynamic characteristics

VSS = 0 V; VDD = 2.5 V to 6.0 V; VLCD = VDD − 2.5 V to VDD − 6.0 V; Tamb = −40 °C to +85 °C; unless otherwise speciﬁed. [1]

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Clock

fclk

clock frequency

normal mode;

VDD = 5 V

[2]

125

200

315

kHz

power saving mode;

VDD = 3.5 V

kHz

tclk(H)

HIGH-level clock time

µs

tclk(L)

LOW-level clock time

µs

tPD(SYNC_N)

SYNC propagation delay

400

tSYNC_NL

SYNC LOW time

µs

tPD(drv)

driver propagation delay

with test loads;

VLCD = VDD − 5 V

--30

µs

I2C-bus

tBUF

bus free time between a STOP and

START condition

4.7

µs

tHD;STA

hold time (repeated) START condition

4.0

µs

tLOW

low period of the SCL clock

4.7

µs

tHIGH

high period of the SCL clock

4.0

µs

tSU;STA

set-up time for a repeated START

condition

4.7

µs

tHD;DAT

data hold time

tSU;DAT

data set-up time

250

rise time of both SDA and SCL signals

1.0

µs

fall time of both SDA and SCL signals

300

tSU;STO

set-up time for STOP condition

4.7

µs

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