ADP8863ACPZ-R7 datasheet(4/48 Pages) AD

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ADP8863

Rev. 0 | Page 4 of 48

Parameter

Symbol

Test Conditions/Comments

Min

Typ

Max

Unit

Output Voltage Threshold

VOUT

Exit Soft Start

VOUT(START)

VOUT rising

0.92 × VIN

Short-Circuit Protection

VOUT(SC)

VOUT falling

0.55 × VIN

Output Overvoltage Protection

VOVP

Activation Level

5.8

OVP Recovery Hysteresis

VOVP(HYS)

500

Thermal Shutdown

Threshold

TSD

150

°C

Hysteresis

TSD(HYS)

°C

Isolation from Input to Output

During Fault

IOUTLKG

VIN = 5.5 V, VOUT = 0 V, Bit nSTBY = 0

1.5

μA

Time to Validate a Fault

tFAULT

μs

I2C INTERFACE

Operating VDDIO Voltage

VDDIO

5.5

Logic Low Input2

VIL

VIN = 3.6 V

0.6

Logic High Input3

VIH

VIN = 3.6 V

1.30

I2C TIMING SPECIFICATIONS

Guaranteed by design

Delay from Reset Deassertion to

I2C Access

tRESET

μs

SCL Frequency

fSCL

400

kHz

SCL High Time

tHIGH

0.6

μs

SCL Low Time

tLOW

1.3

μs

Setup Time

Data

tSU, DAT

100

Repeated Start

tSU, STA

0.6

μs

Stop Condition

tSU, STO

0.6

μs

Hold Time

Data

tHD, DAT

0.9

μs

Start/Repeated Start

tHD, STA

0.6

μs

Bus Free Time (Stop and Start

Conditions)

tBUF

1.3

μs

Rise Time (SCL and SDA)

20 + 0.1 CB

300

Fall Time (SCL and SDA)

20 + 0.1 CB

300

Pulse Width of Suppressed Spike

tSP

Capacitive Load per Bus Line

400

1 Current source matching is calculated by dividing the difference between the maximum and minimum current from the sum of the maximum and minimum.

2 VIL is a function of the input voltage. See

in the

section for typical values over operating ranges.

Figure 15

Typical Performance Characteristics

3 VIH is a function of the input voltage. See

in the

section for typical values over operating ranges.

I2C TIMING DIAGRAM

SDA

SCL

S = START CONDITION

Sr = REPEATED START CONDITION

P = STOP CONDITION

tLOW

tHD, DAT

tHIGH

tSU, DAT

tSU, STA

tHD, STA

tSP

tSU, STO

tBUF

Figure 2. I2C Interface Timing Diagram

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