HT45R22E datasheet(39/72 Pages) HOLTEK

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HT45R22E

Rev. 1.00

March 17, 2010

signal is generated and the Timer/Event Counter will re-

load the value already loaded into the preload register

and continue counting. The interrupt can be disabled by

ensuring that the Timer/Event Counter Interrupt Enable

bit in the corresponding Interrupt Control Register is re-

set to zero.

As the TCn pin is shared with an I/O pin, to ensure that

the pin is configured to operate as a pulse width capture

pin, two things have to happen. The first is to ensure that

the Operating Mode Select bits in the Timer Control

width capture Mode, the second is to ensure that the

port control register configures the pin as an input.

Prescaler

Bits T0PSC0~T0PSC2 of the TMR0C register can be

used to define a division ratio for the internal clock

source of the Timer/Event Counter enabling longer time

out periods to be setup.

PFD Function

The Programmable Frequency Divider provides a

means of producing a variable frequency output suitable

for applications, such as piezo-buzzer driving or other

interfaces requiring a precise frequency generator.

Depending upon which device is used, there is either a

single output, PFD, or a complimentary output pair, PFD

and PFD. As the pins are shared with I/O pins, the func-

tion is selected using the CTRL0 register. Note that the

PFD pin is the inverse of the PFD pin generating a com-

plementary output and supplying more power to con-

nected interfaces such as buzzers. The PFDEN[1:0] in

CTRL0 register can select a single PFD pin or the com-

plimentary pair PFD and PFD for those devices with

dual outputs.

The Timer/Event Counter overflow signal is the clock

source for the PFD function, which is controlled by

PFDCS bit in CTRL0. For applicable devices the clock

source can come from either Timer/Event Counter 0 or

Timer/Event Counter 1. The output frequency is con-

trolled by loading the required values into the timer

prescaler and timer registers to give the required divi-

sion ratio. The counter will begin to count-up from this

preload register value until full, at which point an over-

flow signal is generated, causing both the PFD and PFD

outputs to change state. The counter will then be auto-

matically reloaded with the preload register value and

continue counting-up.

If the CTRL0 register has selected the PFD function,

then for both PFD outputs to operate, it is essential for

the Port A control register PAC, to setup the PFD pins as

outputs. If only one pin is setup as an output, the other

pin can still be used as a normal data input pin. How-

ever, if both pins are setup as inputs then the PFD will

not function. For devices with dual outputs the PFD out-

puts will only be activated if bit PA0 is set high. For de-

vices with a single PFD output, bit PA1 must be set high

to activate the PFD. These output data bits can be used

as the on/off control bit for the PFD outputs. Note that

the PFD outputs will all be low if the output data bit is

cleared to zero.

T i m e r O v e r f l o w

P F D C l o c k

P A 0 D a t a

P F D O u t p u t a t P A 0

PFD Function - Single Output

T i m e r O v e r f l o w

P F D C l o c k

P A 0 o r P A 1 D a t a

P F D O u t p u t a t P A 0

P F D O u t p u t a t P A 1

PFD Function - Complementary Outputs

HT45R22E Datasheet(PDF) 39 Page - Holtek Semiconductor Inc

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